What techniques to reduce EMI noise from a SMPS?

[FusionITR]

Are emi issues all in the layout or are there design techniques/emi filters that can reduce EMI noise?

On the buck SMPS I designed, under light/no load there is no EMI noise at all, but under about 50+ mA load it starts to have (barely) audible noise. If there is a low cost solution I would like to reduce this noise.

Does than ESR of the L or C on the output filter play a role in EMI noise? What about the ESR or the mosfet?

 

[crutschow]

Are you talking about audible (sound) noise or EMI (ElectroMagnetic Interference). They are entirely different.

 

[FusionITR]

Are you talking about audible (sound) noise or EMI (ElectroMagnetic Interference). They are entirely different.

It'a audible noise, but I thought the noise was from EMI being generated about the power supply.

The noise is in the khz range, and I'm sure it has to do with the switching load current because the noise level increases with increasing load current. The output ripple is about 100mVpp at about 4khz depending on the load.

 

[Hero999]

Sound can be minimised by operating at an ultrasonic frequency but not completely. You are using an audible switching frequency which is not good because it will produce an audible noise.

EMI can be minimised by proper filtering.

 

[FusionITR]

Sound can be minimised by operating at an ultrasonic frequency but not completely. You are using an audible switching frequency which is not good because it will produce an audible noise.

EMI can be minimised by proper filtering.

The switching frequency is actually ~200khz, well beyond audible frequency.

Where do I need to apply the filtering and what kind of filter?

 

[crutschow]

EMI has nothing to do with audible noise.

It doens't make sense that the ripple is 4kHz if the switching frequency is 200kHz. You may have some sort of oscillation in the feedback loop.

 

[FusionITR]

EMI has nothing to do with audible noise.

It doens't make sense that the ripple is 4kHz if the switching frequency is 200kHz. You may have some sort of oscillation in the feedback loop.

The 4khz make sense since the period matches the number of pulses it takes to keep the output voltage from falling below the feedback of the sampling network. Hard to explain but I'll post some waveforms later when I get home.

 

[crutschow]

Even if you only sample at a 4kHz rate you should still not see such a ripple. I suspect your feedback loop is not properly compensated and unstable. What type of feedback compensation are you using (lead-lag, lag, fuzzy logic, none, etc.)?

 

[FusionITR]

Even if you only sample at a 4kHz rate you should still not see such a ripple. I suspect your feedback loop is not properly compensated and unstable. What type of feedback compensation are you using (lead-lag, lag, fuzzy logic, none, etc.)?

Here is the type of compensation I am using:

**broken link removed**

Ignore the missing diode in the schematic, its there in the real circuit and the real schematic.

I don't know why my loop wouldn't be stable, I have done simulations and bode plot analysis. Theoretically it should be stable although I have no network analyzer to test it.

 

[schmitt trigger]

If you are using a current-mode controller PWM (like the 3842), you will require slope compensation to prevent sub-harmonic oscillation.

 

[FusionITR]

If you are using a current-mode controller PWM (like the 3842), you will require slope compensation to prevent sub-harmonic oscillation.

It's voltage mode control, the TL1451.

 

[crutschow]

So what sampling frequency were you referring to? All I see is a linear analog feedback loop feeding a PWM operating at 200KHz.

 

[FusionITR]

Waveforms

Here are some waveforms:

Output voltage, CH1 is DC coupled and CH2 is AC coupled.

100 Ohm load:
**broken link removed**

33 Ohm load:
**broken link removed**

Vref and VFB, both AC coupled:
**broken link removed**

VFB and the Vswitch to the mosfet:
**broken link removed**

Zoomed in you can see the pulses are tiny pulsewidths when VFB is below vref and the pulses are gone when vfb > vref. Waveforms make sense.

**broken link removed**

**broken link removed**

 

[crutschow]

The loop appears to be doing limit-cycle oscillations. When properly stabilized, the unit will operate with a constant output pulse-width with a steady output voltage regulated at Vref. The only ripple will be due to the 200kHz switching frequency.

How did you simulate the loop? Can you post your simulation loop with parameter values? Was the PWM simulated with a linear gain block? If you used a gain of one for the PWM gain block, that likely will give you an incorrect simulation, since a PWM generally has an input-to-to output gain significantly greater than one. This PWM gain has to be calculated from the PWM internal chip parameters and the ratio of the input to output voltages. It is not explicitly given in the data sheet

Also state the R & C circuit values and input and output voltages for the circuit.

 

[Ubergeek63]

i hate the loops ... i try to use constant on time variable frequency controllers when ever i can. they might get into the audio at low loads or even sub audio at no load, but they are ALWAYS stable.

a bonus is it is easy to see good values to use if you are not so worried about frequency ... the inductor can be chosen for peak current and the capacitor for the ripple.

dan

 

[schmitt trigger]

It is definitively misbehaving, working in bursts. This will require some troubleshooting.
As Carl mentions, it appears the error amp is doing wall-to-wall oscillations.
Can you put a scope probe on the error amp's output?

Also;
Does the burst repetition rate changes with:
-input voltage?
-load current?

 

[FusionITR]

The loop appears to be doing limit-cycle oscillations. When properly stabilized, the unit will operate with a constant output pulse-width with a steady output voltage regulated at Vref. The only ripple will be due to the 200kHz switching frequency.

How did you simulate the loop? Can you post your simulation loop with parameter values? Was the PWM simulated with a linear gain block? If you used a gain of one for the PWM gain block, that likely will give you an incorrect simulation, since a PWM generally has an input-to-to output gain significantly greater than one. This PWM gain has to be calculated from the PWM internal chip parameters and the ratio of the input to output voltages. It is not explicitly given in the data sheet

Also state the R & C circuit values and input and output voltages for the circuit.

I will post simulation schematics for open loop when I get home later tonight from work and explain how I modeled it. Yes you are right though, I may not have modeled it correctly.

If you want something to work with for now though I'll tell you my component values:

L = 680uH ESR=2.6,
Cout = 100u ESR=0.5
Vref (from the TL1451A) = 1.26
FB resistors was chosen so Vo = 3.3

For the compensation values-
R=300k,
C1=1.3pF (connecting the input and output of the EA)
C2=1n (series with the 300k)

 

[FusionITR]

It is definitively misbehaving, working in bursts. This will require some troubleshooting.
As Carl mentions, it appears the error amp is doing wall-to-wall oscillations.
Can you put a scope probe on the error amp's output?

Also;
Does the burst repetition rate changes with:
-input voltage?
-load current?

I'll post screenshots of the EA output tonight.

The burst changes with load current, I have not tried varying the input voltage yet. The input voltage is about 15V (from a 9VDC wall wart).

 

[schmitt trigger]

I'll post screenshots of the EA output tonight.

The burst changes with load current, I have not tried varying the input voltage yet. The input voltage is about 15V (from a 9VDC wall wart).

OOOps something else to check. The wall-wart output voltage.

I'm not saying this is the root cause, but it has happened to me (twice) before, so here it goes........as the converter starts drawing a load, the wall-wart voltage drops so much that the controller enters UVLO mode. Now, with the near-zero load, the wall-wart voltage increases and recharges its bulk cap until the controler starts again, and the cycle repeats itself.

Should be fairly easy to check with your scope.

 

[crutschow]

I also need the value of the FB resistors that determine the output voltage since that affects the loop gain.