What does BRA do?

[jpanhalt]

I have been studying the enhanced mid-range instructions, specifically "PIC1XF1XXX Software Migration" (DS41375A ©2009) from Microchip.

Most of the descriptions seem pretty clear, except I find the description of BRA confusing:
View attachment 61397
I have highlighted three phrases, and ask "in the same way" as what?

A little searching on Google did not yield any good examples. Can anyone here provide some examples of how Bra operates differently than GoTo to give a different outcome? With reference to the example from Microchip, why not make the first instance "GoTo Label" instead of "Goto $-1" ? How does it then differ from "Bra Label"?

John

 

[Nigel Goodwin]

It's clearly explained in the datasheet - it's a relative jump instead of an absolute one.

Goto Label - jumps to the address 'label' (assuming it's in the same 2K page).

Goto $-1 - jumps back to the previous address, no different to the above (and is an assembler instruction, not code), generates 'goto address' exactly as above does.

Bra Label - does a relative jump, but has the HUGE advantage that being a relative jump it's not affected by paging, so as long as the target is within the limited range (+/-127 or so) then you can ignore paging constraints.

I use Bra ALL the time now I've switched to the enhanced 16F series, but particularly within loops - jumping back in a loop will fail with Goto if it has to cross a page boundary. This can easily happen as you add more code and it gets longer.

 

[Pommie]

I don't see any advantage at all to using bra as opposed to goto.

Mike.

 

[Ian Rogers]

Goto is a two word instruction and BRA is a single....... same as Call is two and RCall is one....

 

[Nigel Goodwin]

I don't see any advantage at all to using bra as opposed to goto.

What about the paging concerns with goto?.

 

[Pommie]

Both goto and bra are 1 word instructions and the paging advantage is so small that it's non existent. Microchip would have been better using it, the opcode, for something else.

Mike.

 

[jpanhalt]

Thank you both for the comments. Some of my reading on university sites (e.g., MIT.edu) indicated one major reason for introducing Bra was because it adds commonality with other versions of Assembly. In fact, one non-MPASM assembler for PIC's has allowed that mnemonic for years. One author went so far as to say that the minimalistic approach Microchip has used in its advertising by stressing the low number of instructions in its RISC is waning.

One advantage I thought Bra might have would be its use over a page boundary, albeit with less range than Brw. In other words, you could avoid using Pagesel, but you would still be limited by the range. I did not see that as a particularly huge advantage; although, I will start using Bra just to show I tried to read the datasheet.

In any event, I found the description confusing, since a common use of goto is like in the "relative-branch" example with goto $-1. Mike, your words were still ringing in my ears when I read that. Thanks for confirming that functionally from my perspective of writing the code, there is not a huge difference.


John

 

[duffy]

Thanks for the heads up about damn page boundary issues. Last time I had that problem was on a Motorola 6805, thirty years ago. I usually use an 18F series but recently I've gotten a project that needs a little 14 pin chip with a bunch of lookup tables and a logic cell, so I'm using a 16F1503.

 

[jpanhalt]

@duffy, I am not sure what importance the word issue has. The MIT discussion forum commented on the same thing. Nevertheless, both goto and bra take two instruction cycles.

John

edit: FYI, my writing for the 16F1519 is progressing after taking several days to get up the nerve. It is nice not to worry about program memory, at least not yet. Brw will be a definite plus, I think, as I will have some graphics tables.

 

[Nigel Goodwin]

Both goto and bra are 1 word instructions and the paging advantage is so small that it's non existent.

I would disagree strongly, removing one of the major concerns with paging problems is a VERY useful feature of it.

I presume Ian was actually referring to the instruction time, where Goto takes two cycles - although I'm not sure if Bra takes one or two?.

 

[jpanhalt]

The datasheet is pretty clear. Bra takes two cycles (p. 272).

John

 

[Nigel Goodwin]

The datasheet is pretty clear. Bra takes two cycles (p. 272).

I presumed the datasheet was clear - but I've never been concerned enough to look

 

[Ian Rogers]

They both are two cycles.... But goto is a double word instruction and bra is a single word instruction...

If I use the btfss / c instruction AND use a goto as the skipped instruction.. The PC seems to cock up a little.... (The manual said that a nop is executed IF the goto or call is within a page boundary... Difficult to remember I thought )....

 

[jpanhalt]

I have not read that GoTo as the skipped instruction causes a problem. That would seem to be a fairly common construct. In fact, I just wrote it for a power-on sequence. Should I add a NOP?

In my search this morning (and last night!) before posting here, I came across an interesting and related discussion of using assembler mnemonics that expand to more than one instruction.

Here is a link: **broken link removed**

<snip>
Actually, the extra memory isn't the problem. Rather, look at what happens if one of those multi-line macros is called by a 'btfsc' or btfss' or 'incfsz' instructions. You would think that the entire instruction that is represented by one of those macros would be skipped in its entirety. Of course, that won't happen. Instead, only the first line of the macro is skipped.

This leads to some interesting debug sessions if you aren't aware of it.

I use some of these special mnemonics all of the time, along with a
bunch of my own one-line macros. But the rule of thumb that I always
try to follow is that I use ONLY one-line macros and ONLY one-line
special mnemonics. When I say 'one line', what I mean is that the
instruction or macro expands to a single line of code.<snip>

That particular note was by Dwayne Reid. Olin Lathrop responded just before his response. I found the thread more interesting than most.

John

 

[Ian Rogers]

No... You don't... the chip does...It only come apparent when simulating / debugging... The code runs as normal... Take this snippet.

decf AREG
btfss AREG      ; when this is evaluated...IF the next instruction is a two word instruction.... then this command is 3 cycles
goto SOMEWHERE ; the debugger whinges here " no code generated " where in actually there is a nop only if the page has not been breached.

Its far easier to use the BRA, BC, BNC... for debugging purposes.

 

[jpanhalt]

Thanks for the advice and follow up. I might be able to give it a test this evening.

John

 

[Pommie]

We seem to be talking at crossed purposes.

On the 18 series BRA has the advantage of using 1 word instead of two.

On the newer 16 series both are 1 word and the only advantage is the fact BRA can cross page boundaries. However, I don't see this as much of an advantage. I never allow code to move over page boundaries as it grows/shrinks as this is asking for bugs. Better to allocate routines to certain pages and call appropriately. Granted that if a loop crosses a page there is no problem but what if the start of the routine crosses a boundary?

Mike.

 

[Ian Rogers]

Mike.. Can you see why C was invented.....

 

[Pommie]

That's why C is pretty much all I use these days.

Mike.

 

[jpanhalt]

They both are two cycles.... But goto is a double word instruction and bra is a single word instruction...

I am completely confused. Maybe I am not the only one. On many sites, there seems to be confusion between instruction cycles and instructions words. I think it is clear from the datasheets how many instruction cycles are used for Bra and Goto. It is much less clear how many words are used for each.

First off, I am not sure what the significance of the number of words is, if the number of instruction cycles is the same.

Second, searches on 2-word, two-word, instruction cycle word, instruction word size, two word instruction, and so forth were unrewarding. (Actually, there was one return , but it dealt with the 18F series.) The datasheets for 12F5xx, 12F683, 16F151x return nothing. I can see that in the 12F5xx series, the 12 bit instruction might be too short for some instructions, and the datasheet diagram showing how the PC is constructed from the opcode and status bits is suggestive of more complexity. But, the other chips I checked all have 14-bit opcodes.

How can one determine from Microchip, which instructions use one word and which use two words? What is the operational significance of a two-word, two-cycle instruction versus a one-word, two-cycle operation that does the same thing?

John