VHDL

This program takes two 4 bit binary inputs, multiplies them and gives the output in BCD. Since the blanks don't show, i use . to represent blanks for easier reading

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity BCDMUL2 is
port( EN : in std_logic;
A, B : in std_logic_vector(3 downto 0);
X : out std_logic_vector(7 downto 0));
end BCDMUL2;

architecture BEHAVIOR of BCDMUL2 is
...signal BIN : std_logic_vector(7 downto 0);
...signal BCD1, BCD0: std_logic_vector(3 downto 0);

begin
...process(EN, A, B)
begin
...BCD1 <= "0000";
...if (EN = '1') then
......BIN <= ("0000" & A) * B;
......for i in 0 to 7 loop
.........if (BIN > "00001001") then
............BIN <= BIN - "00001010";
............BCD1<= BCD1 + "0001";
.........end if;
......end loop;
......BCD0 <= BIN(3 downto 0);
...else
......BCD1 <= "0000";
......BCD0 <= "0000";
...end if;
...X <= BCD1 & BCD0;
...end process;
end BEHAVIOR;
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I could compile them using Max Plus 2 but when i try to do a waveform simulation, it keeps having input oscillation errors when en = 1. The problem was most probably caused by these statements inside the for loop.

if (BIN > "00001001") then
...BIN <= BIN - "00001010"; (can make assignments this way?)
...BCD1<= BCD1 + "0001";
end if;


I am not sure any VHDL experts out there can figure out the problem. Just giving it a shot. Thanks anyway.

Are you trying to write compact code or are you just messing arround with VHDL?
"For loops" are horribly inefficient when it comes to device fitting. I would use a case statement
to do the conversion. As far as your code goes I simulated it ns got the same results you did.
It has some thing to do with the way the the addar is implemented in the VHDL libraries.
I have gotten similar errors on several other projects. It is usually due to a signal not having
a default value. This one has me stumped.