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VHDL

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wuchy143

Member
Hi All,

I think I'm having a bonehead moment and wanted to touch base with any FPGA guys. I'm trying to write a simple glue logic CPLD and since I've never used VHDL before I'm a little confused.

My confusion rests with the following statement contained inside of "architecture" after "begin".

Statement:
Code:
      irq0_cpld_cpu_1 <= '1';
So I take it that this, no matter what, will always set "irq_cpld_cpu_1" to a "1". Why not just use:

Code:
      irq0_cpld_cpu_1 = '1';


What is the point of using the "<"? I must be missing something.


Thanks!
 

kubeek

Well-Known Member
Most Helpful Member
A single = means equal to used in if statements etc.
<= is a signal assignment
:= is a variable assignment
 
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