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Abel to VHDL

drkidd22

Member
I'm trying to convert some CPLD code from Abel into VHDL.

I have the below lines and I'm trying wrap my head around it. I've never used Abel, but I'm familiar with C for programming micros.

Inputs and outputs I can understand, the only thing I'm not clear with is the istype. I could not find an 'input' attribute on Lattice's Abel reference manual and was wondering if anyone here has any idea what it is.

for istype 'com'; the reference manual mentions that 'com' is a Combinational output, what does this really mean? Does it just mean that it is an output result of combination of inputs?

Are nodes simply wires that can be attached to pins and other input declarations?

The declaration of D0-D7 is of 'istype 'reg_d. Seems like a flip-flop declaration for each node.

XEN looks simply like an 8-bit register.

What I don't understand are the bottom three lines of the equation:

OUT.CLK = SPI0_SCLK;
XEN.D = OUT.Q;
XEN.CLK = SPI0_CS3;[/CODE]

Other then setting up the pins on VHDL i'm stuck at the equations section.

Code:
//inputs
SPI0_CS3                    Pin 92        istype 'input';

// outputs
SPI0_MISO                Pin 66        istype 'com';

//Nodes
D0,D1,D2,D3,D4,D5,D6,D7        Node istype 'reg_d';

XEN = [Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7];

OUT = [D7..D0];

equations


D0.D = (!SPI0_CS3 & SPI0_MOSI) # (SPI0_CS3 & D0.Q);
D1.D = (!SPI0_CS3 & D0.Q) # (SPI0_CS3 & D1.Q);
D2.D = (!SPI0_CS3 & D1.Q) # (SPI0_CS3 & D2.Q);
D3.D = (!SPI0_CS3 & D2.Q) # (SPI0_CS3 & D3.Q);
D4.D = (!SPI0_CS3 & D3.Q) # (SPI0_CS3 & D4.Q);
D5.D = (!SPI0_CS3 & D4.Q) # (SPI0_CS3 & D5.Q);
D6.D = (!SPI0_CS3 & D5.Q) # (SPI0_CS3 & D6.Q);
D7.D = (!SPI0_CS3 & D6.Q) # (SPI0_CS3 & D7.Q);
OUT.CLK = SPI0_SCLK;

XEN.D = OUT.Q;
XEN.CLK = SPI0_CS3;
 
Last edited:

rjenkinsgb

Well-Known Member
Most Helpful Member
It's many years since I have written anything in that system..
From what I can see, it's a shift register (the Dn parts) with a parallel output latch, the XEN part.

XEN / OUT relate to eight identical D latches, using the signals defined in the square brackets; each D fed from a shift register Q.

If the SPIO_CS3 input is low, data is clocked in to the shift register via SPIO_CLK and SPIO_MOSI
(And with that CS signal high, each D is fed from its own Q so the state is retained).

When SPIO_CS3 returns high, that (via XEN.CLK) loads the output latches from the shift register data.
The overall outputs are from the latches, with the shift register nodes buried.
 

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