FPGA Troubleshooting

[TerryC03]

I'm having difficulties troubleshooting a possible unintended latch. The board I'm testing with is an Altera DE2-115. I'm using the platform designer and the VHDL code that I had to enter was just the component and ports:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity de2_test_proj is
port(
    clock_50: in std_logic;
    reset: in std_logic;
    gpio: out std_logic_vector(1 downto 0); -- Access to GPIO(0 - 1)?
    ledr: out std_logic_vector(1 downto 0);
    sw: in std_logic_vector(1 downto 0);
    --hex0, hex1, hex2, hex3: out std_logic_vector(7 downto 0);
    lcd_data: inout std_logic_vector(7 downto 0);
    lcd_blon: out std_logic;
    lcd_on: out std_logic;
    lcd_en: out std_logic;
    lcd_rs: out std_logic;
    lcd_rw: out std_logic
    );
end entity;

architecture behavioral of de2_test_proj is
 
    component de2_proj is
        port (
            clk_clk                                 : in    std_logic                    := 'X';             -- clk
            gpio_pio_external_connection_export     : out   std_logic_vector(1 downto 0);                    -- export
            led_pio_external_connection_export      : out   std_logic_vector(1 downto 0) := (others => 'X');                    -- export
--                hex0_pio_external_connection_export     : out   std_logic_vector(7 downto 0);                    -- export
--            hex1_pio_external_connection_export     : out   std_logic_vector(7 downto 0);                    -- export
--            hex2_pio_external_connection_export     : out   std_logic_vector(7 downto 0);                    -- export
--            hex3_pio_external_connection_export     : out   std_logic_vector(7 downto 0);                     -- export
            reset_reset_n                           : in    std_logic                    := 'X';             -- reset_n
            sw_pio_external_connection_export       : in    std_logic_vector(1 downto 0) := (others => 'X'); -- export
            character_lcd_0_external_interface_DATA : inout std_logic_vector(7 downto 0) := (others => 'X'); -- DATA
            character_lcd_0_external_interface_ON   : out   std_logic;                                       -- ON
            character_lcd_0_external_interface_BLON : out   std_logic;                                       -- BLON
            character_lcd_0_external_interface_EN   : out   std_logic;                                       -- EN
            character_lcd_0_external_interface_RS   : out   std_logic;                                       -- RS
            character_lcd_0_external_interface_RW   : out   std_logic                                        -- RW
        );
    end component de2_proj;
begin
    u0 : component de2_proj
        port map (
            clk_clk                                 => clock_50,                                 --                                clk.clk
            gpio_pio_external_connection_export     => gpio(1 downto 0),     --       gpio_pio_external_connection.export
            led_pio_external_connection_export      => ledr(1 downto 0),      --        led_pio_external_connection.export
--                hex0_pio_external_connection_export     => hex0(7 downto 0),     --       hex0_pio_external_connection.export
--            hex1_pio_external_connection_export     => hex1(7 downto 0),     --       hex1_pio_external_connection.export
--            hex2_pio_external_connection_export     => hex2(7 downto 0),     --       hex2_pio_external_connection.export
--            hex3_pio_external_connection_export     => hex3(7 downto 0),      --       hex3_pio_external_connection.export
            reset_reset_n                           => '1',                           --                              reset.reset_n
            sw_pio_external_connection_export       => sw(1 downto 0),       --         sw_pio_external_connection.export
            character_lcd_0_external_interface_DATA => lcd_data(7 downto 0), -- character_lcd_0_external_interface.DATA
            character_lcd_0_external_interface_ON   => lcd_on,   --                                   .ON
            character_lcd_0_external_interface_BLON => lcd_blon, --                                   .BLON
            character_lcd_0_external_interface_EN   => lcd_en,   --                                   .EN
            character_lcd_0_external_interface_RS   => lcd_rs,   --                                   .RS
            character_lcd_0_external_interface_RW   => lcd_rw    --                                   .RW
        );

end architecture;

I commented out the 7-segs (hex) because the issue is causing the ledr14 to go out unintentionally; this is the issue I'm having. Is it the code, or possibly the .qsys file?

 

[TerryC03]

Come to find out, it was both the .qsys file and the VHDL code. The bit width was larger than I needed for the 7-segment displays; I didn't use all of the required bits. I changed the components within the platform designer from 7 bits, to 6. For those who want to see the changes:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity de2_test_proj is
port(
    clock_50: in std_logic;
    reset: in std_logic;
    gpio: out std_logic_vector(1 downto 0); -- Access to GPIO(0 - 1)?
    ledr: out std_logic_vector(1 downto 0);
    sw: in std_logic_vector(1 downto 0);
    hex0, hex1, hex2, hex3: out std_logic_vector(6 downto 0);
    lcd_data: inout std_logic_vector(7 downto 0);
    lcd_blon: out std_logic;
    lcd_on: out std_logic;
    lcd_en: out std_logic;
    lcd_rs: out std_logic;
    lcd_rw: out std_logic
    );
end entity;

architecture behavioral of de2_test_proj is
  
    component de2_proj is
        port (
            clk_clk                                 : in    std_logic                    := 'X';             -- clk
            gpio_pio_external_connection_export     : out   std_logic_vector(1 downto 0);                    -- export
            led_pio_external_connection_export      : out   std_logic_vector(1 downto 0) := (others => '1');                    -- export
                hex0_pio_external_connection_export     : out   std_logic_vector(6 downto 0);                    -- export
            hex1_pio_external_connection_export     : out   std_logic_vector(6 downto 0);                    -- export
            hex2_pio_external_connection_export     : out   std_logic_vector(6 downto 0);                    -- export
            hex3_pio_external_connection_export     : out   std_logic_vector(6 downto 0);                     -- export
            reset_reset_n                           : in    std_logic                    := 'X';             -- reset_n
            sw_pio_external_connection_export       : in    std_logic_vector(1 downto 0) := (others => 'X'); -- export
            character_lcd_0_external_interface_DATA : inout std_logic_vector(7 downto 0) := (others => 'X'); -- DATA
            character_lcd_0_external_interface_ON   : out   std_logic;                                       -- ON
            character_lcd_0_external_interface_BLON : out   std_logic;                                       -- BLON
            character_lcd_0_external_interface_EN   : out   std_logic;                                       -- EN
            character_lcd_0_external_interface_RS   : out   std_logic;                                       -- RS
            character_lcd_0_external_interface_RW   : out   std_logic                                        -- RW
        );
    end component de2_proj;
begin
    u0 : component de2_proj
        port map (
            clk_clk                                 => clock_50,                                 --                                clk.clk
            gpio_pio_external_connection_export     => gpio(1 downto 0),     --       gpio_pio_external_connection.export
            led_pio_external_connection_export      => ledr(1 downto 0),      --        led_pio_external_connection.export
                hex0_pio_external_connection_export     => hex0(6 downto 0),     --       hex0_pio_external_connection.export
            hex1_pio_external_connection_export     => hex1(6 downto 0),     --       hex1_pio_external_connection.export
            hex2_pio_external_connection_export     => hex2(6 downto 0),     --       hex2_pio_external_connection.export
            hex3_pio_external_connection_export     => hex3(6 downto 0),      --       hex3_pio_external_connection.export
            reset_reset_n                           => '1',                           --                              reset.reset_n
            sw_pio_external_connection_export       => sw(1 downto 0),       --         sw_pio_external_connection.export
            character_lcd_0_external_interface_DATA => lcd_data(7 downto 0), -- character_lcd_0_external_interface.DATA
            character_lcd_0_external_interface_ON   => lcd_on,   --                                   .ON
            character_lcd_0_external_interface_BLON => lcd_blon, --                                   .BLON
            character_lcd_0_external_interface_EN   => lcd_en,   --                                   .EN
            character_lcd_0_external_interface_RS   => lcd_rs,   --                                   .RS
            character_lcd_0_external_interface_RW   => lcd_rw    --                                   .RW
        );

end architecture;