Unused port in hierarchical block in LTspice

[R_ZH]

Hello everyone,

I'm doing parasitic capacitance simulation of a SiC half bridge power module. I made a hierarchical block which represents the MOSFET in each switching position. But when I tried to run the simulation, a warning occurred, saying the Tj_MOSFET port in the block was unused, I don't know why it happened since I already connected a voltage source as the case temperature and also the thermal resistance according to the datasheet to that port. All the .asc, .asy, .lib files as well as the warning and netlist screenshot have been attached here. Does anybody have idea how to fix the problem? Any help would be appreciated.

Best regards and thanks in advance!
Runze

 

[simonbramble]

Hi Runze

Here goes...

Delete the 2 modules in Power Module.asc. Go into LTspice and open one of the .lib files (you need to look in the bottom right corner to find (All Files *.*). Right click over the .subckt statement and click Create Symbol. This will create the .asy symbol for you.

Do the same for the other .lib file.

You now have 2 .asy symbols.

Click on the AND gate symbol in the LTspice top menu and navigate to the [Autogenerated] directory. Your new symbols should be in there.

Now open up your CAS480M12HM3.asc file and place these symbols on the schematic. Personally I would delete the original ones just in case they have an error. Right click over each of the ports (g, d, s etc) and select Port Type Bidirectional for each of the ports. These are the ports you want to bring to the outside world in your hierachical schematic. I think you missed out this last bit, because I could not see any ports in your original component.

Go into Windows Explorer and delete CAS480M12HM3.asy (this is your old symbol - you are going to create a new one)

In the menu bar, go to Hierarchy -> Open this sheet's symbol... then select Yes when it offers to create one. This will create a new symbol

Go into the Power Module and place your newly created symbol in the 2 places on your schematic

Run. I can see the gate going up and the Source following it, so it looks like it works with no error messages

The attached has got all this done for you. It works on my machine

Simon Bramble

 

[R_ZH]

Thank you so much for your entire work and answer in details, Simon. I think it should work well and I'll have a look.

 

[eTech]

Hello everyone,

I'm doing parasitic capacitance simulation of a SiC half bridge power module. I made a hierarchical block which represents the MOSFET in each switching position. But when I tried to run the simulation, a warning occurred, saying the Tj_MOSFET port in the block was unused, I don't know why it happened since I already connected a voltage source as the case temperature and also the thermal resistance according to the datasheet to that port. All the .asc, .asy, .lib files as well as the warning and netlist screenshot have been attached here. Does anybody have idea how to fix the problem? Any help would be appreciated.

Best regards and thanks in advance!
Runze

There is a hidden character in the CAS480M12HM3.asy symbol label name Tj_MOSFET
So, to fix it:

1. open the CAS480M12HM3.asy symbol file in LTspice.
2. rht-clk the Ti_MOSFET label.
3. Clear (erase) the label name Tj_MOSFET
4. Re-type the label name Tj_MOSFET
5. Save the symbol.

Done..

 

[R_ZH]

Yes, indeed. I also got that idea. It works quite well. Thanks a lot!