TheOne
New Member
I found this in the projects section, and looking quite simple to build for a beginner, I wondered how good the regulation would be.
https://www.electro-tech-online.com/threads/searching.176/
So once again I fired up my simulator and made some measurements. The regulation at full voltage (15V@1A) wasn't bad at 0.4%. This figure got worse as the voltage was lowered while maintaining 1A current. (I disconnected the current limit for the measurements). Looking at the circuit, I wondered what simple modification could improve the performance? The first obvious thing I spotted was the 1K resistor in the long-tail pair. So I decided to replace this with a constant current source (for obvious reasons). A simple way is to operate a Jfet at it's Idss current by tying the gate to source. This is about 10mA for the Jfet used.
After doing this, I evaluated the performance again near the lowest voltage and the highest voltage setting. This time the % Voltage regulation improved to 0.32% at about 15V and quite a bit to 0.4% from the original 8.7% at about 7V. Ripple rejection ratio improvement was less spectacular to 29dB from 21dB
If someone on this forum actually constructed this PSU, it would be interesting to get feedback regarding the performance before and after the proposed mod.
One last thing, I reduced the value of the current sensing resistor as I could not get a full 1A before the foldback kicked in.
https://www.electro-tech-online.com/threads/searching.176/
So once again I fired up my simulator and made some measurements. The regulation at full voltage (15V@1A) wasn't bad at 0.4%. This figure got worse as the voltage was lowered while maintaining 1A current. (I disconnected the current limit for the measurements). Looking at the circuit, I wondered what simple modification could improve the performance? The first obvious thing I spotted was the 1K resistor in the long-tail pair. So I decided to replace this with a constant current source (for obvious reasons). A simple way is to operate a Jfet at it's Idss current by tying the gate to source. This is about 10mA for the Jfet used.
After doing this, I evaluated the performance again near the lowest voltage and the highest voltage setting. This time the % Voltage regulation improved to 0.32% at about 15V and quite a bit to 0.4% from the original 8.7% at about 7V. Ripple rejection ratio improvement was less spectacular to 29dB from 21dB
If someone on this forum actually constructed this PSU, it would be interesting to get feedback regarding the performance before and after the proposed mod.
One last thing, I reduced the value of the current sensing resistor as I could not get a full 1A before the foldback kicked in.