Sorry, I don't think that circuit will really cut it. Where the input voltage is > Vcc (e.g. 12V in, 5V Vcc), the totem pole output will be either 5V or 0V, the FET VGS = -7 or -12, which will result in an always on FET. Also watch out for the self-destructive nature of that configuration (ie inverting totem pole) - it's possible for both transistors to conduct simultaneously.
I've attached an example level translation schematic if you want to play around with it. It is set up to operate with a ~200kHz PWM source, and requires a logic level drivable FET. C1, R1 & D3 set the gate operating range to roughly between Vin+0.6 to Vin-5. All the other components are to reduce the turn-on surge due to C1 charging and turning on the FET; the inrush can also be decreased dramatically by sending a few pulses of low duty cycle PWM which will get the cap operating where it should very quickly.
You may find 31kHz may be is too low for a small value inductor.
EDIT: a 5V1 or 5V6 zener should be placed on the PWM source for protection from the initial cap charge spike of the circuit I've attached.