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Hello. Simple Time-Delay circuits are well known. I need to restrict a varying larger pulse (a few ms but not constant) to a smaller fixed pulse of around 0.8 ms ( anyway, <1 ms). How do I do this?
Thanks
M
You could use gates from a 4093 quad schmitt NAND.
Assuming the wanted signal is a positive pulse:
Connect the signal to one input of a gate.
Also connect it to both inputs of a second gate (so as an inverter) and connect the output of that via a resistor to the second input of the first gate.
Add a capacitor from that second input to 0V, and a diode across the resistor, cathode to the cap.
(Off the top of my head, I'd expect 10K and 10nF to be roughly in the ballpark for that type of pulse length).
You could use a resistor + preset to make it adjustable.
Function:
At the instant the signal goes high, both inputs of the first gate will become high so its output goes low.
At the same time, the inverted signal will start discharging the cap on the second input at a speed dependant on the RC value.
When that voltage drops to the lower schmitt threshold, the second input switches low and the gate output becomes high again.
You can use another gate with both inputs connected together as an inverter to make the output pulse also positive going. (Or put it at the input if you want the overall circuit to work with a low going edge).
Do not connect a cap directly to an input pin, use a series R from the
cap to the pin, to limit discharge current when part is powered down.
Depends on way part is powered down, so safe (for part) way of getting
cap discharged.
Hello experts, I got general question of maximum input capacitor value for CMOS logic (e.g. HC, AHC, HCT family) input pin. Sometimes, we add capacitor at
@JRW:
Thank you, all. This helps.
Actually, I need a short -ve final pulse. But the principal you describe is what I'm after (I ask various experts who re-arrange things and something else goes wrong. This is true. I admit I personally am hopeless at this).
So could it be as simple as this:
The long +ve pulse comes in to 4093 at A1 and A2. Q1 goes to 0v (please confirm or rule out) and so to the main circuit.
But this lasts 0v for too long. So (this is where you may put me right, if I'm wrong) connect Q1 also to the +ve long pulse via the RC. Diode needed?
There are two 4093 gates for the basic function.
I've drawn it out. (ignore the "DT" suffix, any normal 4093 will work).
This is the minimal circuit, taking a positive pulse in and giving a negative pulse out.
Another gate can be used as an inverter (both inputs linked, like the left hand one) to invert either the input or output.
I've added the protection resistor after the cap, as Dandak mentioned; it's good practice though not likely to be needed with such small capacitor values.
OP, you should sim the circuit using 4093 as it has wide variation in
trip levels of input, hence wide pulse delay, so for this circuit large
variation over T and V of resulting pulse regeneration, hence width.
This, from datasheet, shows the strong dependence on Vp, and Vp varies ":
Or just use a heat gun and a variable power supply and do some bench
characterization.
If this is a one off design then you could easily trim with R1 and / or C1.
If this needs better accuracy use a dual comparator, one sensing RC V,, use the other
in a AND or NAND configuration.
The 4093 is a NAND gate; both inputs must be high for the output to go low.
Or, consider it as either input being low will force the output high.
The operating sequence is:
Idle - input 5 low, output 4 high.
Via the inverter 1,2,3 the capacitor is fully charged so 6 is high.
Start of input pulse - 5 high, 4 low. 6 still high. Capacitor starts to discharge as 3 is now low.
Pulse limit - when the cap discharges enough, 6 switches low and 4 goes high again.
It remains in that state until the input goes low again.
Once the input goes low, 3 goes high and quickly recharges the timing cap via the diode.
It will not be an ultra-precise duration pulse, but for many things the precise duration is not important as long as its in an appropriate range. Delays of this general style have been used in digital electronics for decades.
A quick test of timing variation is to take the natural ln ratio of worst case
min to max Vp. So using just room temp, no supply variation, precision Vdd
of 5V we have :
So pile onto that T and V and passive tolerances and T sensitivities looks like 2:1 or higher
probably norm.
So again if one off design, go for it, if a production design just make sure 100% or higher
variation is tolerable. or use a comparator with a known Vref.....and there are comparators with
onboard Vrefs....
If timing is actually critical, then the simplest approach is to use half a 4098 dual monostable; those have a typical 5% device to device time tolerance guarantee a worst-case device to device variation of 10% when operating on a 5V supply.
Use the "positive edge triggered" configuration and also connect the input signal to the reset input, if you want shorter pulses to not be extended.
That also gives both high and low pulses from the Q and /Q outputs.
They do however need a fast, clean input edge, unlike the 4093 based design, which can handle fairly slow transitions.
Using comparators and separate discharge devices just seems to be way over the top when there are ICs that can do it all in one.
Thank you very much. The subtlety had escaped me. At input +ve, output (4) goes low because cap is temporarily holding 6 high; "temporarily" being the required short pulse (67% of C1.R1 as time).
The circuit is called a leading-edge one-shot. But it ought to be defined for all conditions with tolerances for High input.
They do make dual 1-shot IC's but as shown gates with a diode RC can also serve this function for slow pulse and fast diode reset or a dual NOR set/reset Flip flop with a NOR inverter to Reset after T = 0.7 RC approximately.
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