Hi everyone!I'm about to start a new a design and I want to ask for some help.. The design will be a pcb as host (like a motherboard) that will control and receive data from 10 (identical) pcbs (daughterboards). Each daughterboard pcb, will have 2 FPGAs which will collect data from some ASICs and they will send the acquired data to a master FPGA located on the motherboard. So, the master FPGA will be receiving data from 20 FPGAs and i was wondering what kind of serial protocol to use for their communication. I was thinking of SPI, any other ideas? Thank you for your time.
Actually, i'm not really familiar with other serial protocols that's why i wanted some help.. To hear some ideas and study about the pros and cons of each to decide which is best for my design.
I2C has its advantages and disadvantages. The main advantage is that all of your devices can be connected to the same 2 wires going back to your controller. Each device is then addressed individually in software.
The disadvantages are that it can be slower compared to other serial protocols and - from memory - has a limited transmission (wire) length.
Physically, RS422/RS485 are multidrop differential with good speed and distance. Since 1 master & multiple slaves, half duplex is fine. Logically, a standard async protocol is the easy way out, pending data volume. I'm not seeing how much data each slave uploads and how often is has to do it, nor what distances are between everybody. Overall, somewhat vague... <<<)))
Hi again. The amount of data the slaves upload will be, at most, about 27-30 KBytes each and the overall distance won't be more than 0.5 meter. I don't know yet how often, it depends on many things waiting to find out but i guess about every 1-2 seconds.
Hi again. The amount of data the slaves upload will be, at most, about 27-30 KBytes each and the overall distance won't be more than 0.5 meter. I don't know yet how often, it depends on many things waiting to find out but i guess about every 1-2 seconds.
Normally it will be much less than that, this the maximum amount of data but i have to cover that aspect too. Each FPGA will be collecting result data from some ASICs under test (i was thinking to store the data in a ram inside the FPGAs) and when all the FPGAs have done collecting the data, they will inform the master to start the transfer. When the transfer has been completed a new cycle will be begin for all slaves and so on.
Normally it will be much less than that, this the maximum amount of data but i have to cover that aspect too. Each FPGA will be collecting result data from some ASICs under test (i was thinking to store the data in a ram inside the FPGAs) and when all the FPGAs have done collecting the data, they will inform the master to start the transfer. When the transfer has been completed a new cycle will be begin for all slaves and so on.
The data processing will be done through a labview application but that's another issue. Right now i'm focusing on the communication between the FPGAs.
10 units at 30+kBps (Always worst case the data flow..) = 300+kBps :: 3000+kbps = 3+ Mbps. Lucky you, RS422/RS485 has an ~6.1 Mbps limit. Good thing, that's raw data flow... no formatting/packetizing OR protocol overheads.
I'll hat tip to Nigel, but in a different angle: use uCs as data accumulators to format and (hopefully well) compress the data. Upload the compressed streams then expand and process. You may not have to go this far, but it's an option if raw streaming doesn't cut it. G.H... <<<)))