I'll show you how to use LTSpice to analyze a Schmitt trigger; not how to build one out of CMOS elements.
First, consider the following noisy input, V(in). It is a slow ramp with a sinusoidal noise riding on it. I feed it to three cascaded CMOS inverters, and plot the voltage at V(out1), V(out2), and V(out3). Even though each inverter adds gain, that does square the edges, but it doesn't get rid of the multiple edges caused by the amplified noise source...
Compare the plot above to the one below where I added positive feedback from the second inverter V(out2) (which is in step with the input signal) to the input. R1 and R2 form a voltage divider, so the feedback signal is about 20% of the output step of 3V. Note that eliminates the multiple edges.
Furthermore, look at the two cursors I placed on V(in). Note that up-going trip point is about 261mV higher than the down-going trip point, meaning that the circuit now has hysteresis, which provides the ability to discriminate against the ~100mV of noise riding on the ramp.
This is how a Schmitt Trigger works. I was able to simulate its behavior in LTSpice, and show its salient points. Your job is to get correct NMOS and PMOS models (ones that have channel length and channel width parameters) for the specific CMOS process you are designing for, and to find a way to make a Schmitt Trigger that doesn't utilize 100K resistors...