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Rising edge detector

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It is still best to have a conceptual block diagram with timing if you want to invent something, rather than have accidental failures and learn by fire method.

The one shot is your clock with retriggerable functions.

It is Always better to get help on topology than low level gate issues with the wrong implementation, assuming the idea is sound.
 
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You may need two separate AND functions, but you still cannot just tie the two outputs together unless both outputs will always be in the same state. If the two outputs are different then they will fight each other. At best, the voltage of the two mismatched states will be half the operating voltage. What you will not get is the clean rising edge into the clock pin of your flipflops.

If you need to tie the outputs of the two gates together, you need another gate to do it. If you need to OR them, a CD4001 is a quad, 2-input OR Gate. There may be other options depending on what you really need to do.

After yesterdays reply I looked at 4081 data sheet and saw that the output was a 'totem pole' type. I could either use diodes or an "or" gate like you said. Rather than sprinkling diodes all over the place, think 'or gate' is the way to go.
I'm very green at this stuff and am slowly learning, this project is the reason I took on the learning process. Thanks for the reply.
 
It is still best to have a conceptual block diagram with timing if you want to invent something, rather than have accidental failures and learn by fire method.

The one shot is your clock with retriggerable functions.

It is Always better to get help on topology than low level gate issues with the wrong implementation, assuming the idea is sound.

Believe me this is the end of an over twenty year odyssey. I've done my homework, built the mechanical part of it, and actually ran the machines at work for 13 years. Own every set of DIY plans, magazine articles and most theory books available on the subject of edm.

The 4538 is just being used as an "off" timer. And it is setup to be a nonretriggerable one shot. The 'off' time is needed in the edm process to allow the dielectric to renter the spark gap and flush out the debris to allow the next spark cycle.

If I remember correctly the first replies to my different threads on this subject you said a spark would have to be a real high voltage to even span the gap. But that was wrong, arc welding, plasma cutting and both forms of edm are done all the time every day at the same or lower voltages and larger gaps than what I'm doing. Some of us know electronics and some of us know metal working processes.

Instead of making discouraging remarks why not help? Ronv, Ronsimpson, Reloadron, ChrisP58 and others have given help and encouragement in my on going project. But there have been others, like you that have said nothing but doom of it. Sorry if this seems harsh, just that when it gets closer to actually working after all this time help is more important than criticism to me. The basic idea is very sound, even if not to you.
 
I had no idea this was for EDM in the beginning. Obviously a contact electrode with 1V/um is all that is needed but gap determines how much energy heat flux is in the arc surface. Is there any time when the electrodes stick?

But I would think m you want to know how much energy is being stored for each charge and discharge and have some kind of timing diagram to validate any design.
You may be familiar with what is needed , but I am not a mind reader.

I could help if you can communicate some of the requirements, that I outlined. I've never failed at any design when I started with a spec.... with over a hundred designs.
 
If what you want is (a AND b) or (c AND d) , then you're in luck. You can do it all with NAND gates.

This is because, if you invert the state of the inputs and outputs, the AND function becomes the OR function.

You can use a CD4011 quad NAND gate at each of your three locations and be done. Make sure you tie both inputs of the unused gate to GND or Vcc to keep it from oscillating.
 
The reason I went with and gates is two fold. Biggest one is that the "clocking" (been told that's not the correct term but the guy that said that had no term for it) is coming from comparators that would still be in a 'high' state. By wrapping the Q and notQ around and into the next expected 'clock' signal in the 'and' gate it allows the first comparators 'high' to be ignored. Second reason is to prevent a "race" condition from ever taking place. Was told (by the same guy that told me 'clock' was wrong) that the S and R pins should be used instead of the clock. But that would not allow the correct starting configuration to be chosen, a 50 - 50 chance it would be correct at turn on.

My original idea for all of the clock inputs on these was using edge detectors after the comparators. But that still needed either an 'or' gate or a diode 'or'.
 
Your design has no means for sensing Shorts (current) and charge voltage with no inputs for Boost, so it will be lacking in performance with complex plasma loads and electrode resolution.

I would highly recommend Mr Ananian's design (which I posted) over this and urge you to contact him for revisions.
 
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Tony the schematic shown is only one part of the whole thing, the pulse generator circuit. The ram servo unit takes care of the gap distance and detecting shorts in the gap. The ram circuit is a completed and tested entity. I'm just trying to up date and improve the spark generation. Most DIY units that they sell plans for either use a RC oscillator type circuit or a simple PWM to control frequency and duty cycle. Both are very fussy as to the correct operator settings and to missing or short in time sparking. Neither type is any where close to the way an industrial machine works in efficiency.

Why do you say that the 4xxx series of logic is prone to electrical noise. Every thing I've read says it is the least noise prone. And by using it I only need one power supply for both the logic and mosfet Vgs. Power efficiency is not an important consideration in this project.
 
I would highly recommend Mr Ananian's design (which I posted) over this and urge you to contact him for revisions.

Tony, Scott Ananian's design is in many ways like mine. If you look at it carefully. But instead of discrete logic chips he is using a micro to do the control, others in the DIY edm community have had very little success using a micro with edm. And even though his stuff has been out there for a good number of years, no one not even Ananian himself has built one to his design. There are many flaws in it the biggest being the high voltages he uses. Not even the industrial machines use those high voltages. His was a thesis design and he was doing it, it seems, without ever having seen a working edm or reading any of the theory books written on the subject.

I've had it for many, many years and it is a dead end. Did you read any of the correspondence between him and the others? There is a reason it was never built or used by anyone. He also doesn't show any of the servo controls or ram drive parts of the design. One thing to his credit is that many of his ideas do come from the Langlois book/magazine articles. As do mine. If you can show me where his is better and how, it may be put into consideration.
 
The Bridge design is basically sound and boost arc to overcome gap or fluid pressure rise in breakdown voltage is a bonus. The higher voltage guarantees triggering of the power arc that follows and does not need to be high current, it can be milliamps compared to Amps of the low voltage . Each discharge energy pulse is directly related to the CV^2, so it would be useful to have a linear control proportional to V^2 with ranges controlled by switchable C values for different metals, where the energy is measured in Joules or Watt-seconds. Now both the Cap and arc will have low ESR and it is recommended to have the Cap ESR much lower than the Arc unless there is a reason to limit current with lossy ESR, but preferable series inductance and pulse width can control current better with lower loss.

I don't have any EDM experience, but it wouldn't take me long to get up to speed. ( although I have diffusion bonding experience for bonding tubes with radial diffusion bonding up 100kA which is more difficult as the diffusion weld goes around the circumference, the welded resistance naturally drops so more power must rise rapidly from start to finish around the circumference of the tubes joined to maintain constant arc temperature.. ( Zirc. shim for Monel Steel tubing for Nuclear reactors, circa '79)

Perhaps with your practical experience ,we can put together a general design spec in a table of values, from which I could generate a feasible design.
1) Joule range; Arc trigger voltage
2) Pulse width range;
2a) cutoff criteria (Joules or Amps, threshold )
3) Pulse Interval range;
4) Materials: brass, steel , alum , copper, SS , tool steel, molyb. etc. variations...
5) EDM methods; RAM, Small Hole, Wire
6) Fluid types;
7) Fluid pressure ;
8) Electrode material, shape , diameter:
9) Electrode Fluid tube design; single hollow tube, tri-tube in 1
10) ??

This may exist already in a concise EDM manual, but items 4+ affect items 1~3 which I can easily design, once defined.

Most of challenges are in the magnetics as in Welders etc and a non-saturated core is critical, which may be a large gapped core, or non-ferrous core
I would choose battery power with a charger to avoid the line pulse currents that will be 10x the average current of a standard line bridge rectifier with 10% ripple.
When I get a chance, I'll read Anadian's thesis.
 
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His is transformer less, so NO galvanic isolation. Higher voltages mean a larger gap thus a less accurate cavity being formed in the part. One of the things edm is used for is mold making and often for the ability to machine square inside corners. Higher voltage will increase the machined radius on an inside corner making it harder to meet part specifications.

All of the numbered items have already been addressed in my project. I'm just asking for help on my switching logic. It should be as simple as possible in design. Which I think I have gotten it too. If an operator of one of these machines had three toggle switches and two voltmeters wired into the circuit and could manipulate the switches fast enough to keep the voltmeters in the correct area of indication, the machine would theoretically work. The former setup is exactly what my circuit is doing. The F/F and mosfet drivers/mosfets are the toggle switches. The comparators are the voltmeters.

The way the circuit should perform by just choosing different cap values in the cap bank, the discharge time or duration will take care of itself automatically. The only time that will need to be selected/set is the off or recouperation time between discharges.

It really seems to me that the main thing you find unworkable in this is I'm not using a PCB CAD program to make my schematics. And that I didn't attend college to learn engineering. I've spent so much time and effort to learn how to do this that at 67 years old if I'm to ever see this run taking the time to learn CAD is just another thing I don't have time to do. There's an old saying, "engineers built the Titanic, an amateur built the ark."
 
The direct line approach is weak owing to the stress on line caps and diodes , same for any transformer coupled method.
The advantage for higher V triggers is not to strike at higher gaps but to allow better thermally conducting fluids to temove detonated material with less temperature variations of arc current.. The arc negative resistance is an avalanche effect which can be well defined by the charge Q as discovered long ago. The postive resistance includes entire path materials from metal to electrodes to semiconductors and coolant plasma. The detonation material will have vastly different requirements dependant on the activation energy of the metal, eg, SS, Cu, Al , Mo , Zi, Ni & alloys. The corner and centre removal of material is highly dependant on the electrode material and duct shapes with 7 hole trillium tubes being the best compared to single hole tubing.

The high thermal conducting fluids also tend to be high electrical insulating or breakdown voltage (BDV) Such as petroleum or Ester based fluids vs water or air and may be 10x under pressure.
 
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Why do you say that the 4xxx series of logic is prone to electrical noise. Every thing I've read says it is the least noise prone. And by using it I only need one power supply for both the logic and mosfet Vgs. Power efficiency is not an important consideration in this project.

For inductive current pulse coupling near signal wires, the best logic noise immunity will by far be shielded twisted pair with the lowest impedance, being differential emitter current mode logic or ECL. The original CMOS is 200 to 500 Ohm logic from 16 to 5V with newer logic families migrating towards 5V and 3.3V logic with near 50 Ohm impedance and most advanced high speed logic being still single ended but now near 25 Ohm such as in Atmel's I/O using 'ALVC2 family of CMOS. The advantage of not being differential as in ECL, can partly be overcome with CM chokes in an LC common mode filter. It is true 15V HC' logic is more immune than 5V HC' logic, but both inferior to higher current drive, low impedance logic with controlled transmission lines.

Although CMOS almost current at a 1 or 0, it uses all of its current drive during the switching region to drive the input capacitance which rises during transition voltage, which is also when glitches can occur that might be many Amps nearby coupled to the signal wires if the shielding is poor.

The reasons include that imbalanced single ended logic are prone to noise on a long cable (>1') is that a large current impulse induces an differential voltage in an unbalanced single transmission line impedance which is largely dependant on shielding and shield quality. This noise increases when closer to noise source, surge current, faster rise times and length of cable. Avalanche arc rise times are as fast or faster than most logic, and cannot be reduced other than by long paths observed in nature like cloud to earth lightning being <1us but >10ns

Although ground is never 0 Ohms at all frequencies due inductance and transfer impedance of coax, the V=IR noise pulse induced into a 50 Ohm line vs a zero Ohm return line is different therefore a differential voltage, can exist and requires filtering, shielding, and possibly balancing with a differential signal for greatest immunity. It's a little more complicated than Ohm's Law, but coupling of radiated noise or even conducted ground shift noise works better with low impedance logic lines.
 
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