Race condition in LTspice sim of JK flip flop

[Flyback]

Hi,
I am getting race condition problems in the LTspice sim of a Toggle type JK Flip flop as attached.
Do you know the best way to avoid this?

 

[crutschow]

What is the circuit supposed to do?

 

[rjenkinsgb]

The problem is that is not a JK, it is a single gated (flow-through) latch.

See this article; note the symbol against the clock input for a positive edge - which is not detailed in the gate diagram, but complex:

https://www.electronics-tutorials.ws/sequential/seq_2.html

A JK typically has two separate, cascaded latch (cross-connected bistable) sections, the first loaded from the inputs on one state of the clock and the second loaded from the first on the opposite state of the clock, or the first used to hold the input levels and prevent a race condition to the second.

See page 2 of this datasheet for a 74 series JK:

https://www.ti.com/lit/ds/symlink/sn5476.pdf

The lower part with three gates each side is the input latch, the top part with one gate each side is the output latch.

That's a "Master-Slave" JK. A basic JK would use the first section to capture and hold the input levels.

The non- master slave one is often drawn similar to yours, but internally it needs extra logic to make it edge-triggered and not level-controlled on the clock pin.

The master-slave type JK are typically no more complex than an edge-triggered, type because of the hidden input or clock-edge stage needed for the edge trigger.

eg. See the internal diagram of a 7474 edge-triggered "D" latch; page three of this one:

https://www.ti.com/lit/ds/symlink/sn74ls74a.pdf

It still has two separate cross-connected latches, with the lower one just used to freeze the input data for the above part when the clock changes to high level, to give the edge-triggered effect.

 

[alec_t]

All four gates are identical. Make one slightly different, e.g. by setting td=3n for one and leave the others at td=2n.