Problems with Battery Tester Circuit

[ADWSystems]

This is a continuation, hopefully the finalization of a long standing project.

It doesn't appear to be working as expected. I suspect a wiring issue but it could be design. We talked on this in the past and I have simulations, so I don't think its design. It could be the FET, it's been a while since I have worked with discrete FETs.

I have attached to AA batteries, not new so they only read 2.1V total.

When I closed S1 and S2, VbattRet and Vload go to 0.

I have some data points. but what I'm having trouble with is why when S2 is closed, does VbattRet and Vload go to 0?

With S1 open, and S2 open, Vth=1.6V, OpampOut is -12 , VbattRet is 1.67, Vload is 0.93
With S1 closed, and S2 open, Vth=1.6V, OpampOut is -12 , VbattRet is 1.75, Vload is 1.67
With S1 closed, and S2 closed, Vth=1.6V, OpampOut is 24 , VbattRet is 0, Vload is 0

With S1 open, and S2 open, Vth=3V, OpampOut is -12 , VbattRet is 0.93, Vload is 0.93
With S1 closed, and S2 open, Vth=3V, OpampOut is 24 , VbattRet is 1.77, Vload is 1.77
With S1 closed, and S2 closed, Vth=3V, OpampOut is 24 , VbattRet is 0, Vload is 0

Since Rload is between the battery + and ground, and I'm measuring across Rload, I would expect to see a positive voltage. But I read 0. It's acting like a short, but I can't seem to find it. The power supply voltages are stable and correct when VbattRet=0.

Were have I gone wrong with the circuit?

 

[ADWSystems]

What do you think the chances are I smoked the fet? As noted the OpAmpOut voltage -12V and 24V. The FET is a BUZ101S with a max Vgs of +/-20V.

What happens if the source is floating? Does Vgs apply?

 

[rjenkinsgb]

With S1 closed and S1 open, you could have anything up to 24V gate to source on the FET; that may have blown it.

I'd add a series resistor from the op-amp to gate and a 15V zener from gate to source, so the FET gate voltage cannot get too high.
The resistor value should be high enough so you are not taking excess current from the opamp with 9V across the resistor; eg. 3k3

 

[ADWSystems]

The circuit is designed to test NiCad battery packs, ranging from a single cell to 20 cells. The drain voltage will vary from 1 to ~26V (1V for 1 dead cell and 26 for 20 1.3V charged cells). The source voltage will be equal to the number of cells being testing (1V to 20V in 1V steps).

How do I keep the output of the opamp from exceeding the Vgs max limit while also being able to test 1-20 cells? Is it possible?

 

[rjenkinsgb]

You don't limit the output of the opamp, you limit the gate-source voltage as I mentioned in the last answer.

That's why you need the resistor as well as the zener; the "excess" voltage above the zener limit will be dropped by the resistor. When in normal operation, the gate current is zero so the resistor will have little effect.

Though, you may need to add a small capacitor (100pF ?) across R4 to prevent oscillation.

 

[ADWSystems]

I still need to stop and work all the way through the new development, its implications and effects. I plan to work through that tonight.

If S2 is open (load not connected) will it matter what the gate-source voltage is? If the source is floating, what is the measured Vgs, and does it make a difference?

 

[ADWSystems]

rjenkinsgb, I think I have run into a snag with your plan to add a zener/resistor from gate to source. IIRC, this circuit is basically a constant current source based on the current flowing through the FET then through RLoad, based on Vload = Vth = 1.0V * number of cells in the pack being tested. If additional current is added to Rload at the source of the FET (noted as VLoad) then the current through the FET and Rload will no longer be correct as controlled by opamp.

 

[ADWSystems]

Could I buffer Vload and connect the zener to the output of the buffer op amp?

Would this work?

 

[rjenkinsgb]

The zener needs to be between gate and source, to protect that; not in series with the gate.

When the circuit is operating with both switches closed, the FET will conduct as needed and the zener will have no effect at all.
It purely protects the gate when the circuit is not operating normally.

 

[ADWSystems]

The zener needs to be between gate and source, to protect that; not in series with the gate.

When the circuit is operating with both switches closed, the FET will conduct as needed and the zener will have no effect at all.
It purely protects the gate when the circuit is not operating normally.

That is not true. As VbattRet drops and approaches Vth (or Vload) OpAmpOut will increase to reduce the resistance of the FET. OpAmpOut will start at -12V drawing current from Rload through the Zener (problem #1) and rise to +24V but be clipped at 15V by the zener and start conducting through Rload (problem #2). The ONLY current through Rload can be that through the FET, or the accuracy and measurements will be useless trash.

The zener cannot be connected directly to the FET source from the gate/opamp output. There can be no contribution of current through Rload by any other point. With that given, how do you suggest to prevent the gate-source voltage from exceeding the Vgs limit?

As you stated, the point of the zener is to clamp Vg to less than 20V (15V or so based on using a 15V zener diode) above Vs. The opamp added to the circuit above provides an isolated copy of Vload (aka Vs) as a reference for the zener diode. As OpAmpOut rises to more than 15V above OpAmpVs, the zener will clamp Vg to 15V. I am not sure what value to use for R2 and R3. Actually I debate on the need for R3 and the current should be able to go through the opamp output. Additionally I think a standard diode is also necessary to prevent current flow from ground to the opamp output when the output is at the lower rail (-12V).

 

[rjenkinsgb]

OK, I see what you are trying to do.

You need to move the series resistor to the output of the other opamp, or the zener will have no effect.
That needs a direct connection and the output from the first opamp needs to be limited, so the second one can override the gate voltage via the zener.
Try 4k7 for the series resistor. R3 should not be needed.

Or, if 24V to ground is sufficient, just eliminate the negative supply? That avoids any negative feed via the zener and the positive limit can only put current through the load with the switches off, when nothing is being tested.


Other thoughts: NiCD / NiMH cells may be up to 1.5V immediately after being taken off charge, at full charge.
Retaining the negative and moving all "ground" points to that - reference, load and battery negative - would give more "headroom" for high cell count packs.

You also need an appropriate reference voltage on the setting pot, up to the maximum cell pack end-of-discharge value.
If you are trying to accurately set that, a rotary switch and resistor chain (eg. all 1K between steps plus a regulated feed) may be more suitable, to give repeatable values.

 

[ADWSystems]

Although the FET may be blown, the data points listed have little to do with any of the discussion so far. During some of the tests, I also included an ammeter to see if there was any current draw when the battery related voltages dropped to 0. The ammeter also showed 0. Last night I decided to test the ammeter and fuse. Works OK. 12V power supply, 1k resistor, reads 12mA. Tested against the batteries alone with the same 1k resistor, 0mA and 0V. Turns out one of the batteries had votage but no capacity (no ability to supply even 1mA).

Tonight I will try different batteries, checked with the ammeter first while also dropping 24V to 18V to stay below VgsMax in the event I haven't yet blown the FET.

You need to move the series resistor to the output of the other opamp, or the zener will have no effect.
That needs a direct connection and the output from the first opamp needs to be limited, so the second one can override the gate voltage via the zener.
Try 4k7 for the series resistor. R3 should not be needed.

I will try that. I was working on simulations last night and could not get them to work and I think this is the reason why. (I'm doing simulations because I don't have any 12-18V zeners on hand).

Or, if 24V to ground is sufficient, just eliminate the negative supply? That avoids any negative feed via the zener and the positive limit can only put current through the load with the switches off, when nothing is being tested.

I need to be able to get the opamp output to close to zero for testing a single cell. Below 0V would be better to be able to ensure the FET is completely off. Is -12V overkill? Yes. But for some reason +5/-5/+12 volt power supplies are way more expensive than +5/+12/-12 volt power supplies.

Other thoughts: NiCD / NiMH cells may be up to 1.5V immediately after being taken off charge, at full charge.
Retaining the negative and moving all "ground" points to that - reference, load and battery negative - would give more "headroom" for high cell count packs

Not completely sure what your trying to say or do here. But I think it may not be possible due to the single cell situation as previously mentioned.

You also need an appropriate reference voltage on the setting pot, up to the maximum cell pack end-of-discharge value.
If you are trying to accurately set that, a rotary switch and resistor chain (eg. all 1K between steps plus a regulated feed) may be more suitable, to give repeatable values.

The reference will actually be from a 14 bit DAC and a 4x gain opamp. Plenty of accuracy. (as it's drawn, with the pot referenced to +5V, it could not test more than 4 cell packs and its designed for 20)

 

[ADWSystems]

Although the FET may be blown, the data points listed have little to do with any of the discussion so far. During some of the tests, I also included an ammeter to see if there was any current draw when the battery related voltages dropped to 0. The ammeter also showed 0. Last night I decided to test the ammeter and fuse. Works OK. 12V power supply, 1k resistor, reads 12mA. Tested against the batteries alone with the same 1k resistor, 0mA and 0V. Turns out one of the batteries had votage but no capacity (no ability to supply even 1mA).

Tonight I will try different batteries, checked with the ammeter first while also dropping 24V to 18V to stay below VgsMax in the event I haven't yet blown the FET.


I will try that. I was working on simulations last night and could not get them to work and I think this is the reason why. (I'm doing simulations because I don't have any 12-18V zeners on hand).


I need to be able to get the opamp output to close to zero for testing a single cell. Below 0V would be better to be able to ensure the FET is completely off. Is -12V overkill? Yes. But for some reason +5/-5/+12 volt power supplies are way more expensive than +5/+12/-12 volt power supplies.


Not completely sure what your trying to say or do here. But I think it may not be possible due to the single cell situation as previously mentioned.


The reference will actually be from a 14 bit DAC and a 4x gain opamp. Plenty of accuracy.

 

[ADWSystems]

I reduced the voltage to 18V to stay below VgsMax and changed batteries. As I hypothesized, one of the previous batteries did not have the ability to take a load (voltage cropped to 0 under a 1k load). Upon replacing the batteries with new batteries (well actually used, but I checked that they could/would handle a load), the circuit performed as expected.

I will be building v2, with the zener diode included to clamp the output to less than VgsMax. I believe the zener diode will work to clamp Vg to <15V above Vs, but is there another way? Is there a way to limit the opamp output, or add another stage where the output is limited? I' thin king the circuit would have to work such that stage 2 out = stage 1 out, unless/until stage 1 out >15V above Vs, then clamp to 15V+Vs?

 

[rjenkinsgb]

Another option would be to put the FET in one of the ground positions and use a differential amp circuit to monitor battery voltage?

Or, simpler, use an opto-isolated FET driver.
They use a LED plus photovoltaic cell to produce a completely isolated gate drive; just connect the output between source and gate then drive the LED from the opamp.
You then have an absolute zero influence on overall FET source current no matter what the load, supply voltage or drive conditions.

One example: **broken link removed**

Add a gate-source load resistor to the driver, eg. 1M, and you get a reasonably linear transfer, 0-8V out for 0-5mA LED drive, which should give good proportional control and work well in your system.

 

[ADWSystems]

I'm not sure about the diffamp method.

Opto isolated FET driver is an interesting option. The VOM1271 package may be an issue being only SMD (I'm still stuck in the through hole world).

I don't see in the datasheet how much current is expected to be drawn through the VOM FET connections. Assuming 0 for the moment, I understand how to make the FET connections. I'm confused on the LED connections. The opamp output that will drive the LED, will run from -12V to +24V. Where does the cathode get connected? -12V or ground? If to ground, then Vr is exceeded. If connected to -12V, then it will conduct starting at while the opamp output voltage is negative. Until the opamp output reaches 0 there is no need for FET drive, but I have to have a negative power supply in order to get the opamp to have a 0 output, as the opamp does not have a rail-to-rail output.

 

[rjenkinsgb]

There are various other types of those optos, eg. TLP590B, which has a conventional DIL version.
**broken link removed**

I'd try a series resistor from the opamp to the LED anode, to limit the current - eg. 2K2. Reduce it if there is insufficient drive.
Connect the cathode to 0V and add a reverse diode across the LED, a 1N4148 etc., to protect it from reverse voltage.

 

[ADWSystems]

How would I find an n-channel mosfet with a RdsOn <0.050 ohms and a VgsMax >30V?

 

[rjenkinsgb]

Something like these?
https://uk.rs-online.com/web/p/mosfets/7849215/
https://docs-emea.rs-online.com/webdocs/122f/0900766b8122f79c.pdf

https://uk.rs-online.com/web/p/mosfets/5411247/
https://docs-emea.rs-online.com/webdocs/0791/0900766b807913d5.pdf

https://uk.rs-online.com/web/p/mosfets/4857721/
https://docs-emea.rs-online.com/webdocs/135f/0900766b8135f86c.pdf

 

[ADWSystems]

Nothing like those. Those all have VgsMax of +/-16V. I would need at least 25V, 30V would be best.

This has ALWAYS been my week point. I can make the circuit, but can't find the parts.