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Problem in CMOS differential amplifier design.

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Alex_bam

New Member
Hello,
It's my first attempt to design CMOS Differential amplifier in 0.35um technology using a cadence tool. I search threads related to my problem in this forum but could not able to solve my problem. So I will explain my approach in deriving dimensions of MOSFET's used in it. Moreover, I have also attached my simulation picture for your reference.

I get help from the following reference for calculations:
https://medium.com/@vishnuanugrahith/designing-of-a-cmos-differential-amplifier-68d3d90baae4

Design Parameters:
GBW
= 10M CL= 10pF, Vdd=5V
UnCox=190u A/V^2; UpCox=55u A/V^2;
Vtn=0.8V Vtp=-1V
Slew Rate(SR) :10V/uSec
Vcmax=4.5V ; Vcmin=1.5V (input common mode range)


Step 1 _ Calculating Id:
Id=SR*CL 10V/uSec * 10pF= 100uA

Step 2 - Calculating (W/L) for M3 and M4:
Vds1=Vmax-vthn=4.5-0.8=3.7V
Vds3=Vdd-Vds1=5-3.7=1.3V
Id3=Id/2=50uA
(W/L)= 2*Id3/UpCox*vds3=1.075

Step 3 - Calculating (W/L) for M1 and M2:
gm1=GBW*2*pi*CL
= 10M*2*3.14*10pF
=6.27*10^-4
Id1=Id/2
(W/L)=gm1^2 / 2*Id1*unCox
=20.75

Step 4 _ Calculating (W/L) for M5 and M6:
Vx=(Vmin-Vtn)-Vdsat1
Vdsat1= (2*Id1/UnCox * (W/L)1 )^1/2= 0.16
Vx=0.54
Id5=Id
(W/L) =2*Id5/UnCox * Vx^2= 3.6

Finally, transistor dimensions are:
(W/L)1,2
= 1.07u / 1u
(W/L)3,4 = 20.75u / 1u
(W/L)5,6 = 3.6u / 1u

Differential input Signal:
Freq= 1 Mhz; Amp= 500 mV; Sine DC level= 2V

Differential gain:
= gm2 (ron_n2 || ron_p4)
= 418.5u( 71.73K || 17.04K )
=5.7

1_ I am not getting the output signal according to my calculated gain? I am making mistake in my calculations?
2_ Could anyone comment on my design and mathematical calculations?
3- I am always struggling to find the un*Cox value of MOSFET. after searching in different threads in this and other forums. One way is to find it from betaeff=un*Cox*W/L. But un*Cox changes with changing W/L. So I am always doubtful regarding un*Cox value. Can anybody know the accurate method to find un*Cox value of MOSFET especially using Cadence?

Thanks.
 

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