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Power Mosfet drive techniques

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Optikon

New Member
Hi all,

I have an application where I will be using a power MOSFET (N-Channel) as a switch. I would like this device to transition through its linear region as rapidly as possible and I am contemplating the drive circuit for this.

A typical drive circuit would consist of a low-impedance voltage source as the gate drive where at high frequencies, the lower the source impedance can be, the better. One of the problems for the voltage drive is the gate capacitance to ground(common return) since the moderate output impedance (at higher freq) interacts with that parasitic capacitance (gate charging is slowed).

And for large geometry power devices, this is the worst case since these parasitics tend to be larger. I have in the past designed a push-pull unity gain buffer as the driver that is good out to over 100MHz but I would like to try something else as an alternative this time-round.

I would like to know if anyone has ever experimented with driving devices like this with a current source instead. My line of thinking goes something like the following:

1) A current source is not bothered by the gate capacitance (the one to ground that is) and so the parasitic that limited to voltage source drive is easily overcome.

2) The current source will not like parasitic inductance however, but this is EASY! (Or so I think). The MOS device itself is not inherently inductive other than its leads which, I can keep very very short. I can also lay the design out so that I do not introduce any additional L with the routing/wiring.

3) But alas, some inductance will remain and it should be in the 10's of nH if things go well. This will present an L(dI/dt) effect that will cause a voltage transient that could possibly cause my current source to turn off. I can increase my power supply voltage to a level that will keep my current source working and give acceptable results.

I would somehow need to turn on my current source quickly so it can supply adequate charge to the gate and transition through the gate-charge spec very quickly.

I do not have a schematic yet and I do not have a specific turn on time requirement. I also do not have any special circumstances for the design such as isolation or inductive loads on the drain etc.. I will be driving this system open-loop (On-off style) I don't have a power mos part in mind yet either but it wil be typical of a 100W device with Vth = 2-4V and milli-ohm Rds(ON) with Vgs = 10V.

I am looking for anyones thoughts on trying this method and problems I might encounter. I am very curious to discover what the limiting factors will be. I have read a thread on voltage-controlled versus current controlled transistors and I don't want to go there. Please comment on driving the gate with a current source.


THANKS!!
:D :D :D
 

motion

New Member
I have a few questions on the current source drive technique.

1. You can't exceed the maximum gate to source voltage rating. Once you have supplied enough gate charge to turn ON the device, how can you detect this condition and turn-off the current source before the gate voltage goes beyond the maximum rationg?

2. Have you considered the effect of the miller capacitance effects specially during turn-off?
 

Roff

Well-Known Member
I agree that there are several problems to deal with if you use current drive. Miller capacitance is one of them.
You are going to need peak currents of several amps to get the risetimes you want. This is difficult to do with bipolar transistors, because high current transistors tend to have low Ft and high capacitances, which in turn lead to crappy risetimes.
I'm thinking that a push-pull, common-source MOSFET driver (drains tied together- just a BIG logic inverter) would be your best bet. Look for MOSFETs with Rds<1 ohm and low gate charge. A quick search yielded BSH114 and Si9400DY. You might find better ones. This really looks like current-source drive anyway while the transistors are in saturation.
Drive that pair with push-pull emitter followers (2N2222/2N2907), or with another push-pull MOSFET inverter of smaller geometry.
 

Optikon

New Member
motion said:
I have a few questions on the current source drive technique.

1. You can't exceed the maximum gate to source voltage rating. Once you have supplied enough gate charge to turn ON the device, how can you detect this condition and turn-off the current source before the gate voltage goes beyond the maximum rationg?

2. Have you considered the effect of the miller capacitance effects specially during turn-off?
Yeah, Vgs max might be a problem. I would try and inherently limit the driver from getting near this value. Clamping might work - not sure.

The miller capacitance is precisely why I think a high speed current source could improve response. The design would have to be symmetrical (Bipolar) in the sense that, I can charge miller-C and also discharge it with the high speed driver. I'm not convinced that the idea is worth pursuing yet.

Thanks for your reply!
 

Optikon

New Member
Ron H said:
I agree that there are several problems to deal with if you use current drive. Miller capacitance is one of them.
You are going to need peak currents of several amps to get the risetimes you want. This is difficult to do with bipolar transistors, because high current transistors tend to have low Ft and high capacitances, which in turn lead to crappy risetimes.
I'm thinking that a push-pull, common-source MOSFET driver (drains tied together- just a BIG logic inverter) would be your best bet. Look for MOSFETs with Rds<1 ohm and low gate charge. A quick search yielded BSH114 and Si9400DY. You might find better ones. This really looks like current-source drive anyway while the transistors are in saturation.
Drive that pair with push-pull emitter followers (2N2222/2N2907), or with another push-pull MOSFET inverter of smaller geometry.
Hmm.. yes, I realize that several amps of transient current would be required (those parasitics want alot to give you speed!). Your idea is interesting. Essentially progressively smaller geometry Push-pull drive stages. And all the way at the front end is where the lowly bipolars are that only need to deliver possibly mA at high speeds which is feasible.

In effect, this arrangement would have distributed the current gain-bandwidth more evenly throughout the system of drivers.

Of course, in a design like this, local bypassing is critical since, I don't think I can make my power supplies low-Z out to possibly hundreds of MHz.

Thanks a Meg for your input!
 

Roff

Well-Known Member
Before my previous post a ran some quick sims on the topology I suggested, as well as one where I drove a BF MOSFET with a 10 amp lload (1 ohm, 10v). The gate driver was a behavioral +/-2 amp current source with 10ns rise/fall times. The gate voltage was clamped to +10v and GND with Schottky rectifiers. The resulting voltage waveform was not symmetrical, had lousy rise & fall times, and,of course, would dissipate a lot of unnecessary power. To minimize power dissipation, you have to build current sources with very little headroom if you are going to leave them on after they are clamped. You can try to use common-emitter bipolars and let them saturate for self-clamping, but then you have to figure out how to turn one off before the other turns on, or you'll get smoke from one or both of them (you have to clean out the excess base charge before the transistor will turn off). You can drive the bases of the transistors with differentiators (i.e., AC coupled) if the frequency is fairly low, but you will still have problems finding fast bipolars that can supply several amps.
Maybe you can see how I got to the scaled CMOS inverters solution. As I said, a MOSFET has high output impedance (read constant current ) while it is saturated (saturation in MOSFETs is opposite of saturation in bipolars). They don't suffer storage time problems like bipolars. Using this configuration, you only burn current when you need it - during transitions.
Let us know what you come up with.
 

Roff

Well-Known Member
Good find, O frumious Bandersnatch! Those IC manufacturers are always spoiling the fun for us discrete analog hackers! (This from a guy who designs DRAMs for a living.)
 
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