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Please Help. Crazy signals from a simple circuit.

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PConst167

Member
Friends, I have been struggling with a problem for days now and I am getting frustrated.

I have a simple circuit consisting of a 74HC4040 12bit binary ripple counter, and a 74HC08 AND gate.

I take two outputs from the counter 12 and 11 for example, and feed it into the gate, then look at the output on my oscilloscope.

The output rather than being the AND of both inputs, is rather a superposition of both signals. It's unstable and looks strange.

I have made a video of the scope showing the signals, and also here;s a photo of the circuit set up.

Please help me to find out what is going on. I have tried everything. If the problem was due to the fact that the counter is a ripple counter, then wouldnt I just get some hazards and that;s it? This is really different in that the signal is not stable and flikkers all the time.

Thank you in advance.


 

MikeMl

Well-Known Member
Most Helpful Member
How are you triggering the scope?
Is that a sampling scope?
 
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PConst167

Member
I''m not sure. The scope is a HP 54501A scope. It's in automatic triggering at the moment.... Should I change something ?
 

schmitt trigger

Well-Known Member
It is a sampling scope, which is set in the dot mode, instead of the vector mode. One can see the individual sampling periods as individual dots on the rising and falling edges.

To me, like Mike suspects, it is a problem how you are triggering the scope.

If you have a 4 channel scope, use Ch1 for the slowest counter, Ch2 for the next counter, and finally the Ch3 for the Ch1 AND Ch2 output.
Trigger from Ch1. Adjust the timebase such that you get integer clock periods and thus a stable display.

Also...decouple the 8.0 Mhz oscillator. Protoboards are not good for high frequency circuits, and I strongly suspect that you may have noise which is falsely triggering the counter. That will completely screw up your count.
As a matter of fact, there is A LOT OF NOISE, which one can see as dots jumping high and low.
 

spec

Well-Known Member
Most Helpful Member
Friends, I have been struggling with a problem for days now and I am getting frustrated.

I have a simple circuit consisting of a 74HC4040 12bit binary ripple counter, and a 74HC08 AND gate.

I take two outputs from the counter 12 and 11 for example, and feed it into the gate, then look at the output on my oscilloscope.

The output rather than being the AND of both inputs, is rather a superposition of both signals. It's unstable and looks strange.

I have made a video of the scope showing the signals, and also here;s a photo of the circuit set up.

Please help me to find out what is going on. I have tried everything. If the problem was due to the fact that the counter is a ripple counter, then wouldnt I just get some hazards and that;s it? This is really different in that the signal is not stable and flikkers all the time.
H1 PC,

You say that you are decoding 74HC4040 Q12 (pin 1) and Q11 (pin 15) with one of the 74HC08 and gates, but the picture of your bread-board shows that you are in fact decoding Q12 (pin 1) and Q6 (pin 2).

If you decide Q12 and Q13 the output of the and gate will be a positive pulse with a mark-to-space ratio of 1:3 (you must trigger your scope from the output of the and gate.

Also you must connect at least one of the input pins of each of the three spare and gates in the 74HC08 to 0V.

spec
 

PConst167

Member
H1 PC,

You say that you are decoding 74HC4040 Q12 (pin 1) and Q11 (pin 15) with one of the 74HC08 and gates, but the picture of your bread-board shows that you are in fact decoding Q12 (pin 1) and Q6 (pin 2).

If you decide Q12 and Q13 the output of the and gate will be a positive pulse with a mark-to-space ratio of 1:3 (you must trigger your scope from the output of the and gate.

Also you must connect at least one of the input pins of each of the three spare and gates in the 74HC08 to 0V.

spec
I'm impressed with your sharpness. I changes the pins because the same result is happening for every pin. What do you mean I must trigger it from the output of the and gate ? Please do explain. I have my probe at the output of the AND gate. Is that what you mean ?

I have connected the unused inputs of the AND gate however it didnt change anything so I removed the connections...

In fact, I have tried changing the Hold Off option on the scope, and the waveform shows clearly. However I dont know if changing HoldOff is the right thing, or is it just compensating for the problem in the circuit? What is HoldOff actually doing ? Because it does fix the output waveform,!
 

PConst167

Member
It is a sampling scope, which is set in the dot mode, instead of the vector mode. One can see the individual sampling periods as individual dots on the rising and falling edges.

To me, like Mike suspects, it is a problem how you are triggering the scope.

If you have a 4 channel scope, use Ch1 for the slowest counter, Ch2 for the next counter, and finally the Ch3 for the Ch1 AND Ch2 output.
Trigger from Ch1. Adjust the timebase such that you get integer clock periods and thus a stable display.

Also...decouple the 8.0 Mhz oscillator. Protoboards are not good for high frequency circuits, and I strongly suspect that you may have noise which is falsely triggering the counter. That will completely screw up your count.
As a matter of fact, there is A LOT OF NOISE, which one can see as dots jumping high and low.

I tried changing the HoldOff option on the trigger page, and in fact the waveform started to show correctly. However only a few ranges of HoldOff work. For example triggering at 310us HoldOff displays it correctly, but below that it doesnt.

Also what do you mean by trigger from channel 1? I have channel one at the output of the AND gate. Also what do you mean by adjust the timebase so I have integer clock periods? If the clock period is not an integer will the screen be unstable? I dont understand...
 

spec

Well-Known Member
Most Helpful Member
I'm impressed with your sharpness.
Thank you.:)
I have connected the unused inputs of the AND gate however it didnt change anything so I removed the connections...
You should always define the logic state of unused logic elements, so best put the connections back
I changes the pins because the same result is happening for every pin.
Got you!
What do you mean I must trigger it from the output of the and gate ? Please do explain. I have my probe at the output of the AND gate. Is that what you mean ?
Yes but you must make sure that your scope is triggering from that input channel. Best select a positive trigger.
In fact, I have tried changing the Hold Off option on the scope, and the waveform shows clearly.
That is interesting.
However I dont know if changing HoldOff is the right thing, or is it just compensating for the problem in the circuit?
Yes, a good point
What is HoldOff actually doing ?
Your scope trigger circuit selects a certain voltage or edge of the input waveform to start the time-base ramp which deflects the spot on the face of the scope from left to right at a speed that you select.

That way the waveform displayed is synchronized and does not jitter about.

While the spot is moving from left to right the trigger gate is closed and the scope time-base cannot be re-triggered, but once the trace has reached the right of the display and has then flown back to the left of the display again, the trigger gate opens again and the time-base will be ready for the next trigger event.

Hold-off keeps the trigger gate closed, for a period you select, after the spot has returned to the left of the screen.

spec
 

spec

Well-Known Member
Most Helpful Member
What supply voltage are you using?

What type and value are the decoupling capacitors across the two chips- they should be be ceramic around 100nF.

It looks like you are using an 8MHz oscillator. Is this correct?

Is the oscillator also decoupled with a ceramic capacitor?

What is the output of the oscillator- is it compatible with HC logic or just TTL.

It looks like a square-wave oscillator module- is that correct?

spec
 

spec

Well-Known Member
Most Helpful Member
The physical layout of the chips does not flow. I would suggest that you swap the the location of the gate and the counter so that you do not have the long wire from the Xtal oscillator to the counter.

spec
 

PConst167

Member
What supply voltage are you using?

What type and value are the decoupling capacitors across the two chips- they should be be ceramic around 100nF.

It looks like you are using an 8MHz oscillator. Is this correct?

Is the oscillator also decoupled with a ceramic capacitor?

What is the output of the oscillator- is it compatible with HC logic or just TTL.

It looks like a square-wave oscillator module- is that correct?

spec


My god...................Oh my god :O

I think this crystal might not be CMOS compatible ! The output voltage from it is around 3V. But I am using 74HC which at 5V requires VIO to be 3,8 or something! Let me check this....................I never thought about this!!!! This might be the problem!!!
 

spec

Well-Known Member
Most Helpful Member
Can I suggest that you make a much lower frequency oscillator (a Schmitt inverter gate, a resistor, and a capacitor), say 10KHz and drive the counter with that to test functionality.

spec
 

PConst167

Member
Can I suggest that you make a much lower frequency oscillator (a Schmitt inverter gate, a resistor, and a capacitor), say 10KHz and drive the counter with that to test functionality.

spec

Yes certainly. Im going to do that right now. I can't thank you enough for solving my problem. I'm almost sure this is the problem. In my datasheet it says that at 4.5V the VIH must be at least 3.15V. I am using 5V so its gonna be higher than that. On my scope the waveform coming from the crystal is around 3.2V ! Could this be the problem then ?
 

spec

Well-Known Member
Most Helpful Member
Yes certainly. Im going to do that right now. I can't thank you enough for solving my problem. I'm almost sure this is the problem. In my datasheet it says that at 4.5V the VIH must be at least 3.15V. I am using 5V so its gonna be higher than that. On my scope the waveform coming from the crystal is around 3.2V ! Could this be the problem then ?
Yes, it could well be.

You could try connecting a 1K resistor from the output of the xtal to the 5V line.

But don't get your hopes up too high- faults can be very weird.:eek:

spec
 

PConst167

Member
Hey Friend. I tried connecting the resistor but the problem remained. Well, I think the secret is really the Hold Off. I found the period of the signal, and whenever the HoldOff is a multiple of the period, the waveform stabilizes and makes sense, but whenever it isnt, the waveform gets crazy.

So it's really the HoldOff, plus of course the voltage at the crystal.

Why is hold off doing this? Why is hold off so important for this type of signal ? This signal is not a simple signal. It's periodic but it varies inside the period. Is this the reason why ?
 

spec

Well-Known Member
Most Helpful Member
Hey Friend. I tried connecting the resistor but the problem remained.
Yes, that was along shot afraid.
Have you got any 74HC Schmitt gates like the 74HC14 etc. If so, try one of those between the Xtal and counter clock.

Well, I think the secret is really the Hold Off. I found the period of the signal, and whenever the HoldOff is a multiple of the period, the waveform stabilizes and makes sense, but whenever it isnt, the waveform gets crazy.

So it's really the HoldOff, plus of course the voltage at the crystal.

Why is hold off doing this? Why is hold off so important for this type of signal ? This signal is not a simple signal. It's periodic but it varies inside the period. Is this the reason why ?
My guess, and nothing more, is that the up count binary sequence is being corrupted by something undefined at the moment.

Sorry to say, but I suspect that the hold off stetting is just hiding the corrupted part of the up count sequence.

spec
 
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spec

Well-Known Member
Most Helpful Member
Something does not gel:

(1) You have a 32 bit counter, making a total count of 2^32
(2) You have an 8MHz Xtal, which has a period of 1/8MHz = 125nS
(3) If you work that lot out it means that Q32 should be changing logic level only ever 537 seconds, but Q32 appears to be changing a whole lot faster than that.

spec
 

PConst167

Member
Something does not gel:

(1) You have a 32 bit counter, making a total count of 2^32
(2) You have an 8MHz Xtal, which has a period of 1/8MHz = 125nS
(3) If you work that lot out it means that Q32 should be changing logic level only ever 537 seconds, but Q32 appears to be changing a whole lot faster than that.

spec
My counter is only 12 bits, not 32. Why did you think its 32?
 

spec

Well-Known Member
Most Helpful Member
My counter is only 12 bits, not 32. Why did you think its 32?
Its late here and my brain is not working.:banghead:

If I haven't made another mistake, Q12 output should be changing every 491.52 uS

Is this the case

spec
 
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PConst167

Member
Its late here and my brain is not working.:banghead:

If I haven't made another mistake, Q12 output should be changing every 491.52 uS

Is this the case

spec

The Q12 output divides the 8MHz clock by 2^12 so the period of Q12 is 512us..... You see? Yes the scope shows a period of 512us.........

So I guess we're set ? The problem was the hold off that was out of sync....

My problem started when I was building a circuit to generate composite video sync signals, and the circuit didn't work. Then I tried to work out the problem and disassembled everything and tried probing the counters, and then I saw those crazy waveforms and thought that was the reason why it didnt work.

So now that the counters are really fine, the problem is somewhere else. Probably my circuit contains logic hazards since it was asynchronous.

Do you use Skype or something? Id like to keep contact with you if you wanna be friends and talk electronics :)
 
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