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phase locked loop??

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jovabiot

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hello.i have a question. i'm going to design a bpsk demodulator at 50Mhz with a pll, but i haven't in pspice a pll that works at 100Mhz. How can i do a model of pll that works at this frequency? or where can i obtenin a model?? anyone has one?? thanks
 
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