open collector gates for wired-AND operation

[PG1995]

Hi,

Could you please help me with this query? Thanks for the help!

I understand that when two or more open-collector gates are combined, you get a wired-AND gate. But such a wired-AND gates has negative logic which means it gives HIGH output only when all its inputs are LOW. I agree with the expression on the right which says X=A'B'C'D' where A' means complement of A.

I do not understand why the author is using uncomplemented inputs to derive output expression in subsequent sections. Please see the green highlights where it is said that X=ABCDEFGH and X=ABCDEF.

Is there a mistake in the text, or is it just me? Please guide me.

 

[rjenkinsgb]

The example is using AND gates (not NAND) so there is no inversion involved.

When all the AND gate inputs are high, all the outputs will go high (or rather open) allowing the pullup to set the output level high.

 

[PG1995]

I don't think those are regular AND gates. Notice the symbol in middle of each 'AND' gate. Thanks.

 

[rjenkinsgb]

That symbol indicates they are an open collector type rather than conventional logic with both active high and active low drive.
https://farm8.staticflickr.com/7058/6794892088_6bff89c56c.jpg

 

[KeepItSimpleStupid]

Actually, I've seen wired AND or wired OR with an open collector output.

See this: http://www.revolvy.com/page/Wired-logic-connection

 

[PG1995]

Thank you!

But I don't think that I understand it. The following picture is from the link provided by KeepItSimpleStupid . Both inputs should be LOW to get HIGH at the output X. This is open-collector AND gate. I'm sure that the missing of word 'wired' doesn't make much of a difference.

X = (Input_1)' (Input_2)' where apostrophe denotes complement.

 

[rjenkinsgb]

Those are NAND gates, not AND gates. The dot / small circle on the output represents a signal inversion.
With both inputs connected together they function as simple inverters, with open collector outputs (though they are missing the OC symbol).

With that configuration, both gates need the inputs LOW to give high (open) outputs.

See the various gate type symbols in the article here:
https://whatis.techtarget.com/definition/logic-gate-AND-OR-XOR-NOT-NAND-NOR-and-XNOR

 

[PG1995]

Thank you!

From the discussion, the following is what I have concluded. A wired-AND configuration of inverters is different from open-collector AND gate. A wired-AND configuration of inverters works like a negative-AND gate. An open-collector AND gate has a transistor attached to its output. Please have a look on the picture below. Do I have it correct?

 

[gophert]

I think. You are confused about a Low output being different than no output. In logic speak, a Low is literally a connection to ground. Several of your circuit images are directly connecting a low output to a high output which will short out the output pins and cause catistrophic damage to the component.

 

[rjenkinsgb]

Please have a look on the picture below. Do I have it correct?

Yes, I think you have it spot on correct.

An open collector TTL gate in effect is missing the upper half of the normal totem pole output, so only the pull-down transistor controls the output.

 

[Nigel Goodwin]

A wired-AND configuration of inverters works like a negative-AND gate.

As I told you back in your other thread, it's an OR gate or a NAND (Not-AND) gate, they are the same thing.

 

[rjenkinsgb]

OR gate or a NAND (Not-AND) gate, they are the same thing.

Have to take issue there Nigel.

An OR gate does not invert, a NAND does.

 

[gophert]

Have to take issue there Nigel.

An OR gate does not invert, a NAND does.

I don't think he meant that, I think some parenthesis were needed. NAND and NOT AND are the same thing.

 

[PG1995]

Thank you!

Yes, I think you have it spot on correct.

To be honest, there is still confusion in my mind and most of it comes from how the author has, in my opinion, mixed up the stuff in the given section. Anyway, let's see.

An open collector TTL gate in effect is missing the upper half of the normal totem pole output, so only the pull-down transistor controls the output.

Yes, you are right. In open collector TTL inverter gate R3, Q4 and D2 are missing.

Do you really think that the circuit in FIGURE 2 is correct (Edit: FIGURE 2 from my previous post, post #8)? It says that a normal AND gate is connected to a normal inverter and then there is an open collector transistor attached to the output of inverter.

To get a NAND gate, as Nigel Goodwin pointed out, you can just connect an open collector transistor to the output of normal AND gate as shown below.

Thank you.

 

[Nigel Goodwin]

Have to take issue there Nigel.

An OR gate does not invert, a NAND does.

Sorry for the confusion, they are PHYSICALLY the same thing (or can be).

 

[rjenkinsgb]

Do you really think that the circuit in FIGURE 2 is correct? It says that a normal AND gate is connected to a normal inverter and then there is an open collector transistor attached to the output of inverter.

To get a NAND gate, as @Nigel Goodwin pointed out, you can just connect an open collector transistor to the output of normal AND gate as shown below.

I don't know which is supposed to be figure 2.

An AND gate connected to an inverter with an open collector output is functionally the same as an AND gate plus a transistor (which inverts) to give the open collector output. Each gives NAND function.
(Remember that in reality the external transistor would need resistors between gate & base and base-emitter.)

If the first text refers to an open collector AND, then the double inversion is correct, to retain the overall AND function.

 

[KeepItSimpleStupid]

NAND to quasi OC NAND, all you need is a diode, cathode to gate output. Take the OC output from the Anode.

The output LOW is a bit higher voltage, but it works most of the time.

 

[PG1995]

Thank you!

I don't know which is supposed to be figure 2.

Sorry, I was referring to FIGURE 2 from my earlier post, i.e. post #8.