wuchy143
Member
Hi All,
I have gone through a couple application notes(this forum as well) and what not on thermal considerations for a transistor(or any electrical device that absorbs energy and dissipates it through heat transfer via heatsink, air, copper, etc). I don't need to get down to 128-bit resolution to see if this device is going to operate within it's derating but would like a ball park idea.
Can anyone review and tell me if I'm right or at least in the ball park. I haven't done many thermal stuff due to never doing much high current so please any tips and what not please say. I"m using 2N6388 as my darlington pair npn configuration.
Here are my calculations/thoughts.
My amplifer(2N6388) will at worse case scenario see 10.5V(DC) across it's collector and emitter while driving 500mA. This is fact. So the power that the transistor is absorbing is:
P = V * I = (10.5V * 500mA) = 5.25 Watts dissipated in transistor as heat.
From ON Semi's 2N6388 datasheet (https://www.onsemi.com/pub_link/Collateral/2N6387-D.PDF) you will see that the thermal resistance to the case is 1.92*C/W
So the 1.92*C/W multiplied by the amount of power(5.25W) you will get a temperature increase of 10*C from ambient. In my case ambient is 20*C(68*F) which will increase my junction temperature to 30*C(86*F)
This means that the junction of my transistor will rise up to 30*C when driving 500mA with a 10.5V potential difference between the collector and emitter.
I know from a seat of the pants feeling(I"m about to prototype my circuit anyway but wanted to do out the calculation as well) that I'm fine. The part might get a little warm but wont even requite a real heatsink.
I have two questions:
1. How close am I to the correct rise in temp?
2. In the datasheet which I supplied above in figure 1 there is a power derating graph. I've stared at it for a while and don't "get it". Can anyone de-mystify this graph to me? You can make fun of me for being a dummy
Thanks again all!!!!
I have gone through a couple application notes(this forum as well) and what not on thermal considerations for a transistor(or any electrical device that absorbs energy and dissipates it through heat transfer via heatsink, air, copper, etc). I don't need to get down to 128-bit resolution to see if this device is going to operate within it's derating but would like a ball park idea.
Can anyone review and tell me if I'm right or at least in the ball park. I haven't done many thermal stuff due to never doing much high current so please any tips and what not please say. I"m using 2N6388 as my darlington pair npn configuration.
Here are my calculations/thoughts.
My amplifer(2N6388) will at worse case scenario see 10.5V(DC) across it's collector and emitter while driving 500mA. This is fact. So the power that the transistor is absorbing is:
P = V * I = (10.5V * 500mA) = 5.25 Watts dissipated in transistor as heat.
From ON Semi's 2N6388 datasheet (https://www.onsemi.com/pub_link/Collateral/2N6387-D.PDF) you will see that the thermal resistance to the case is 1.92*C/W
So the 1.92*C/W multiplied by the amount of power(5.25W) you will get a temperature increase of 10*C from ambient. In my case ambient is 20*C(68*F) which will increase my junction temperature to 30*C(86*F)
This means that the junction of my transistor will rise up to 30*C when driving 500mA with a 10.5V potential difference between the collector and emitter.
I know from a seat of the pants feeling(I"m about to prototype my circuit anyway but wanted to do out the calculation as well) that I'm fine. The part might get a little warm but wont even requite a real heatsink.
I have two questions:
1. How close am I to the correct rise in temp?
2. In the datasheet which I supplied above in figure 1 there is a power derating graph. I've stared at it for a while and don't "get it". Can anyone de-mystify this graph to me? You can make fun of me for being a dummy
Thanks again all!!!!