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Thanks !When one side of the NAND latch goes from high-to-low, the opposite side can only go from low-to-high after the delay through the 6 inverting feedback buffers. Thus the two output clocks can never be high at the same time, performing the non-overlapping function.
You are mistaken. The delay through the inverters in the feedback loop insures that there will be no overlap. The clocks are never both high at the same time. Being both low at the same time is okay.This circuit certainly doesn't guarantee non-overlap in the nano-second arena. Depending on the load on each of the two clock phases, there can easily be a small overlap when both are logic level high or logic level low. This may not be important for the circuit you are going to use the clocks in, but is a significant problem, in high speed logic design.
JimW
1. Well, that's general rule, not absolute. The chance of oscillation can be minimized by proper layout and decoupling.Two maybe dumb statements-
1. According to the "Cmos Cookbook", you should never use more than three inverters in series. Due to the possibility of oscillation.
2. Wouldn't it be better to just feed the clock into a flip flop?