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Can someone help me, if this CMOS circuit (attached) implementation is correct? for a Non-overlapping Two-Phase Clock Generator
Below is the schematic diagram of the CMOS logic ckt.
If you compare those, the diagrams shows one as being bufferend and on not.
The unbuffered one is marginally faster, but that is with quite a big capacitive load of 50 pF. With a smaller load, the unbuffered one would be distinctly faster than the buffered one.
The circuit that you have shown relies on the propagation delay to give the timing gap between the phases. The gap* will be around three gate delays, or 30 ns. I don't know if that is enough for your application, as there is usually a reason for a non-overlapping clock, which might need more time.
As the gate delay depends on temperature and supply voltage, you will find the phase gap varying and it could become insufficient.
As an example of non-overlapping clocks, something like this /https://www.onsemi.com/pdf/datasheet/ncv7547-d.pdf
has preset times from one MOSFET turning off to another turning on, called the blanking times, of 1, 2, 3 or 4 μs. That is the time allowed so that you don't get both MOSFETs conducting at the same time, which would short the supply. The smallest time programmed into that IC is 30 times longer than your circuit will give.
*I'm not sure of the correct term for the opposite of overlap.
Looks like there's a small amount of non-overlap, but you'd have to zoom in on the transition points to see how much.
What non-overlay time are you looking for?
If you want a big fat deadband without lotsa gates, a small R-C network will get you microseconds (or tens of nanoseconds) of delay repeatably and cheap. Are you looking for a discrete component circuit or for something within a CPLD or FPGA?
AND - five posts in - what is the clock frequency, and the minimum and maximum deadband times you can work with?
Thanks for all your input, I truly appreciate it. This is just one of our lab experiments, and we needed to do pre-simulation (schematic layout) and post-simulation (cell layout). I'm just seeking some help from the experts to determine if the implemented CMOS circuit provided is correct based on the schematic of the logic circuit.
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