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Non-Overlapping Clock

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Syafiq

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Hi,

Can anyone provide an explanation on how a 2-phase non-overlapping clock works? I've attached a schematic of my clock design. Thanks!
 

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When one side of the NAND latch goes from high-to-low, the opposite side can only go from low-to-high after the delay through the 6 inverting feedback buffers. Thus the two output clocks can never be high at the same time, performing the non-overlapping function.
 
When one side of the NAND latch goes from high-to-low, the opposite side can only go from low-to-high after the delay through the 6 inverting feedback buffers. Thus the two output clocks can never be high at the same time, performing the non-overlapping function.
Thanks !
 
This circuit certainly doesn't guarantee non-overlap in the nano-second arena. Depending on the load on each of the two clock phases, there can easily be a small overlap when both are logic level high or logic level low. This may not be important for the circuit you are going to use the clocks in, but is a significant problem, in high speed logic design.

JimW
 
This circuit certainly doesn't guarantee non-overlap in the nano-second arena. Depending on the load on each of the two clock phases, there can easily be a small overlap when both are logic level high or logic level low. This may not be important for the circuit you are going to use the clocks in, but is a significant problem, in high speed logic design.

JimW
You are mistaken. The delay through the inverters in the feedback loop insures that there will be no overlap. The clocks are never both high at the same time. Being both low at the same time is okay.

Edit: See simulation below.

NO Clock.gif
 
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Well, I stand by my post. Simulating with slow speed CMOS makes the high level overlaps less of a concern. But not necessarily with a free running oscillator with fast inverters. With variances in components and the individual gates in components, the delay through each inverter is not fixed, it is a range. In a worst case design analysis, this variation alone can easily provide high level overlap of 1 to 6 nanoseconds.

Depending on the logic family chosen and the capacitive load on the output clock signals, the rise and fall times themselves can provide or worsen the overlap.

And the statement about simultaneous low signals not being a problem is just bizarre. That would be completely dependent on the circuit. Anytime you have multiple clocks in a circuit, you need to worry about which components use which edges and which asynchronous states. For what the OP is doing, his circuit may be perfectly acceptable, and hopefully your simulation will tell him exactly what he needs to know.

I am probably viewing things too much through the lens of ultra high speed design. And multiclock synchronous circuitry. But it never hurts to mention some concerns.

-Jim
 
Ultra high speed CMOS certainly has much less delay but it still should scale. Do you really understand how this circuit works? If you need to widen the non-overlap gap then you just use more inverters in series until the non-overlap is greater than your process variations or clock loading require. And I would think all inverters on any particular chip would tend to have very similar delay times.

Why is the statement about simultaneous low not being a problem "bizarre"? If simultaneous low is a problem then you just invert the two clocks but then you will get a simultaneous high. Obviously the two clocks will need to be either simultaneous low or simultaneous high. You can pick one or the other for you design but not both.
 
Two maybe dumb statements-
1. According to the "Cmos Cookbook", you should never use more than three inverters in series. Due to the possibility of oscillation.

2. Wouldn't it be better to just feed the clock into a flip flop?
 
Two maybe dumb statements-
1. According to the "Cmos Cookbook", you should never use more than three inverters in series. Due to the possibility of oscillation.

2. Wouldn't it be better to just feed the clock into a flip flop?
1. Well, that's general rule, not absolute. The chance of oscillation can be minimized by proper layout and decoupling.

2. Yes a flip-flop with a couple of NOR gates can be used to give non-overlapping clocks but it reduces the clock frequency by 1/2 which may not be wanted in high clock frequency circuits.
 
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I agree that the multiple oscillators in series are not a problem. Series inverters will not oscillate by themselves without a feedback path. And this circuit has an intentional feedback path synced to the input clock. Unless there is a bad layout, it will not free run oscillate.

And yes crutschow, I know how the circuit works. 30 years ago I knew how the circuit worked. But when someone asks for a non-overlap clock driver circuit the assumption should not be made that they want a circuit that does not overlap the high pulses (or just the low pulses). My first assumption would be that they want matched clock driver circuits that have as close as possible to simultaneous clock transitions. Without any other input that still seems reasonable to me. Maybe you knew that he wanted a slow/medium speed driver circuit that had non-conflicting high times, and it which case, the circuit proposed is fine.

There are still several potential problems with the circuit. One is that it does not work reliably at high frequency input clocks. The variability on the propagation delays of the inverters rapidly approach the low and high periods of the clock. This circuit just wont work reliably at 10 - 50 MHz with standard CMOS inverters. The longer the chain of inverters to seperate the high pulses, the lower the input frequency that it will reliably work at.

The second problem comes into play if the prop delay of the three buffer inverters on one clock drivers are substantially slower than the prop delay of the three series inverters in the the other half. If this difference is equal to the prop delay of the six series inverters, then there is a clock overlap. PROBABLY not a problem if they are from the same logic family, but this can't be guaranteed. Especially if it is a slow logic family like CMOS where the prop delay can be anywhere from 20 ns up to 90ns. This problem requires a lot of things to stack up before it becomes a problem, but it still can be an issue. Especially if this is a mass production design where even a .1% problem is a big deal.

I certainly don't want to turn this into a pissing contest. If this circuit accomplishes what the OP wants, and at the frequency that he wants, then great.

JimW
 
Well, it appears we may be talking apples and oranges. My understanding is for a non-overlapping clock that is used for two-phase logic where you do not want the two clocks high (or low) at the same time. One clock must be low before the other goes high. But you are talking about two clocks with near simultaneous transitions. If you knew how that circuit worked "30 years ago" what was it used for?
 
It is just one of many ways to make a multi-phase set of clock signals. Depending on the design, you might want staggered rise and fall edges, and the high and low overlaps were a good thing. Or an asymmetrical clock in the middle of the high time of a symmetrical clock. Lots of possibilities for multiple clocks. This particular one was a version that nominally used precision delay lines instead of the string of inverters. It was more predictable for the high speed designs. Costly though.

JimW
 
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