Logic circuit....

[AnArKey]

If input A is logic 1, AND input B is logic 1, then output logic 1 on C.

Also, once A is logic 1, even if B drops to logic 0, continue to output logic 1 on C, until A goes to logic 0, THEN go to logic 0 on C.

Basically, B is a interrupt of the logic coming from A, but can only enable or disable entire pulses, without being able to cut them in the middle.

I'm assuming some gates and flip flops can do this, I'm just so rusty I can't remember how.

 

[Roff]

I think this does what you want:
A=clock input to "D flipflop.
B=data input to "D" flipflop.
A and "Q" output from flipflop go to both inputs of an AND gate, whose output is "C".

 

[laroche73]

registers, latches & gates

Ron's correct, except for the last statement. An AND gate would give the correct output, but it's redundant. A negative edge triggered D-type flip-flop is enough. From your description, it sounds like you want a flip-flop, though you may want to review the differences between flip-flops and latches before deciding.

https://www.electro-tech-online.com/threads/schematic-teisco-checkmate-50.3730/

Sorry, I haven't visted this site in a while, just pop in now and then to keep Ron in line. (only on digital, can't hold a candle on analog). - CL

 

[Roff]

Claude, I think you missed something. Look at the bold text below:

If input A is logic 1, AND input B is logic 1, then output logic 1 on C.

Also, once A is logic 1, even if B drops to logic 0, continue to output logic 1 on C, until A goes to logic 0, THEN go to logic 0 on C.

Basically, B is a interrupt of the logic coming from A, but can only enable or disable entire pulses, without being able to cut them in the middle.

I'm assuming some gates and flip flops can do this, I'm just so rusty I can't remember how.

 

[laroche73]

double take

OK. one of us missed something. For a positive-edge triggered flip-flop, a gate (OR) would be needed. It's amazing how confusing simple logic circuits can be.

 

[Roff]

Re: double take

OK. one of us missed something. For a positive-edge triggered flip-flop, a gate (OR) would be needed.

Claude, we're both screwed up. I was thinking AND but typed NAND. An OR gate won't work. I'll edit my original post to reflect the correction.

 

[laroche73]

All this over a misspelling?

Well... that's what I said in the first place. That's the problem with "experts" and "oracles", sometimes they make you doubt your own sanity :wink: . I come from the PLD/FPGA world, where pos/neg clock polarities and flip-flop/latches were trivial choices to make. For the 74xx families, most flip-flops are positive-edge triggered and latches do their thing on negative levels. Btw, the "OR" gate came from substituting the "B" input for "A". Just to be clear, a positive-edge F/F & AND gate or a negative-edge F/F with no gating will work - CL

 

[AnArKey]

I came to the same conclusion, a positive edge triggered D flip flop, with the clock input tied to one input on a AND gate, and the Q output going to the second input on the AND gate. The change of 0->1 at the clock will only carry through the to the final output if D is also 1 at the instant of 0->1 on the clock. If D is 0 at the instant of clock 0->1, Q will be set (or remain) at 0, and the AND gate will output 0.

The negative edge triggered D flip flop however, I don't think will work. If the clock is 0 at any moment, I must be positive the final output is also 0. If clock drops from 1 to 0, while D is 1, that will set Q as 1, which I don't want.

Now I'm having a tough time finding a IC with at least 6 D flip flops, with seperate clocks, and if possible, a common data.

The purpose of this is a fuel injector pulse interrupt, where it will kill a entire pulse only, never able to make a partial pulse. The number of skipped events will be a result of the duty cycle of a PWM signal on the data inputs. 100% duty, all pulses get thruogh, 75% duty, only 75% of the pulses get through. I understand it will be a hit and miss strategy, like flipping a coin, but with 100s of pulses a second, it will balance out. The law of large numbers I think.

I'm probably also going to have two frequency to voltage converters, one for a front wheel speed detector, the other for a rear wheel speed detector, and a voltage comparator of those two outputs. More voltage, more speed disparity, and inferred wheel spin. This voltage will then go into a inverse voltage to PWM conversion (0V=100% duty, more voltage is less duty), which will be fed to the data inputs on all the above flip flops. End result, high speed, electronic, fuel based traction control.

 

[laroche73]

better

The negative edge triggered D flip flop however, I don't think will work. If the clock is 0 at any moment, I must be positive the final output is also 0. If clock drops from 1 to 0, while D is 1, that will set Q as 1, which I don't want.

That's better. Finding an adequate solution depends upon a good description of the problem you're trying to solve.

You're dealing with a low enough frequency for a microcontroller to handle. It can be done with stand alone logic, but learning to work with a micro wouldn't be wasted time. Regardless of how you decide to solve the problem, please post any questions, and share your results. Ron had a better understanding of the semantics than I did, my apologies. - Claude

 

[hates]

i think u can use a delay flipflop