Little help understanding CMOS circuit design.

Question:
Design a 3-input NOR gate. If the PMOS devices are half as conductive as the NMOS devices determine the correct transistor sizes.

I understand how to design the pull up pull down circuit, just unsure about calculating the correct transistor sizes. Thanks

no target supply range, no target threshold , no target power draw at target frequency, no target frequency to specify target power at -- you literally can't be sure what the term "correct" stands here for , relax

Ci139 Im pretty sure the question is just asking to specify the width/length ratio for each transistor using the conduction parameter, Kn = kn'/2 . W/L. Just unsure how to utilise this formula.

i have downloaded a loads of misc FET pdf's - for further studies for SFSeleC3C - i'm shure there're more formulas you'll ever need avail in www ((g.d. weather -- not really into anything right now)) ...
... i actually checked and need to correct - i've diagonal read a lot of docs containing fet formulas but much not stored for offline access /// in atch.'s anything i found more or less related to the field - titles that could reveal the src. doc from web search

cneb97 said:

Question:
Design a 3-input NOR gate. If the PMOS devices are half as conductive as the NMOS devices determine the correct transistor sizes.

I understand how to design the pull up pull down circuit, just unsure about calculating the correct transistor sizes. Thanks

Click to expand...

A NOR has parallel N's, but the Ps are in-series. A single N can discharge the output capacitance. It takes all three Ps to charge the output capacitance. If the ON resistance of an N is 100Ω, what would the ON resistance of a P have to be so that the charge/discharge times are equal?

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as i fuzzily remember then the threshold is not good to had at supply median coz it'd cause instability or issues with multiple input "decoding"/(status/state-)readout - it might've applied to TTL only ?