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Latching CMOS ckt to drive a relay

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electrookie

New Member
Hi all;

In the attached drawing, I am trying to figure if I got it right or not. What I am after is a Logic circuit that will latch upon a certain condition and will not toggle till a reset switch is depressed. I have been searching the web and have pieced together this circuit. I am going to build it next, but thought I would run it up the flag pole for some comments.

The goal is when the 2 inputs (labeled outputs) are high, the flip flop will turn the Q on and the Q' off, the Q will be sent to a relay to turn it on. The 10uf cap and 1M resis on the reset line are to insure power on condition of Q off and Q' on.

If this looks like I got it right, then please do let me know. However, as I suspect, I probably have something wrong here, then your input will be invaluable. I will go build this now and check back later to see if anyone replied and to post my results.

Thanks all in this forum...

OOOPPP's... The AND gates shown are supposed to be NAND gates, so keep this in mind when examining circuit. Thanks again...
 

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electrookie

New Member
Latching CMOS ckt ro drive relay Take 2...

Well, I built it and of course, it doesn't work right. What I get is at power on, Q = 1 and Q' = 0. When I trigger the inputs to the 1st NAND gate, nothing happens. Q's do not swap outputs. When I tried to do the reset, Q became a nice square wave then collapsed back to a 1. Q' stayed 0. If I held reset, Q stays in square wave permanently, it doe's go back to 1 when release reset, after a few seconds of cap charging.

Back to the web to do more searching. If anyone has suggestions or even an entirely different circuit, I would appreciate hearing from you.

Thanks all...
 

vne147

Member
I might be wrong but this is what I see going on in your circuit. To set the output high (the part labeled “To Ckt that energizes relay”), you need to set either pin 5 or 6 high to make pin 4 high. Once pin 4 is high, it also sets pin 8 high on the second OR gate. That in turn sets pins 10 and 6 high which is what gives you the latching effect. The problems I see are first, the LED that is connected to pins 10 and 6 will drive those pins high regardless of circuit state. Also, as for the portion of the circuit connected to pin 9, with the switch open, pin 9 will be high, with the switch closed, pin 9 will be low but pin 8 will remain high and in turn so will pin 10. The bottom line is as long as pin 8 remains high, it doesn't matter what you do with pin 9, pin 10 will remain high too. I’m not sure why those components are there. I could be wrong but would something like this not work (see circuit 1 in the attached schematic)? There is a momentary normally closed switch in between pins 10 and 6. I removed the LED and the other portion of the circuit that was connected to pin 9. When you open the switch pin 6 goes low and as long as pin 5 is low, pin 4 will go low too. That in turn sets pin 8 low and finally pin 10 goes low so that when the momentary switch gets closed again, the circuit will not relatch. It won’t relatch again until both inputs go high. Am I out in left field anybody? If I was doing this project I would also try out the simpler circuit shown in circuit 2. Let me know if you test out either one of these ideas and what happens.
 

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electrookie

New Member
Fault Tripped Latch ckt. - w/Relay

Thanks for the suggestion's vne147. I will get around to trying what you put forth soon as I can get the time too. It is an interesting circuit and I would like to see it work at any rate. The cap & resistor are supposed to ensure the power on state of the circuit is the same every time, which was a good idea also.

For now though, I found another circuit on the net that I whipped up and it seems to work very well, so I will use this one for now. I may go back to the CMOS design if'n & when'n I have a chance to, it just looks cleaner and the rest of the ckt. it is in has those gates extra, not being used.

I will check in again and see if anyone else has any idea's on the original ckt in question. Thanks again...
 

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mneary

New Member
Cannot tell if your gates are AND or OR. AND gates tend to have flat left edges.

In either case, a flip flop is usually made from NAND gates.
 

vne147

Member
Cannot tell if your gates are AND or OR. AND gates tend to have flat left edges.

In either case, a flip flop is usually made from NAND gates.

For the comments I made I assumed that the gate in the upper left hand corner of the schematic was a NAND gate and the other two were OR gates.
 

mneary

New Member
electrorookie has changed the original post. Now he says the gates that almost look like OR gates are really NAND.

A corrected diagram has not been posted. It appears that he wants us to draw his corrections on our own screen. It looks like it would have been an easy problem if the diagram was accurate.
 
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