jk flipflop j and k permanent 0

[whoracle]

hello,
i am new in this forum and have a question. i study physics so i dont know relly much abaout electronic parts.
our prof gave us an electronic schematic. there are several jk-flipflops where only the clock has an input. so imo j and k is always 0. no the task is to find out what the output of a jk flipflop is where j and k have no input, only the clock.

perhaps somebody can help me;-)

thanks

 

[crutschow]

If J and K are both at logic zero, then the output of the FF will not change states.

 

[whoracle]

yes i know. but they are not combined to any signal so they are zero from the beginning. what happens then?

 

[ericgibbs]

Look at this image for a J/K.

Edit:
Sorry, the GIF image will not attach

Now a PNG

 

[whoracle]

View attachment 64503

this is the jk flip flop in out electronic schematic. does this generally make sense?

 

[Grossel]

Hi.

A JK with non-connected J and K inputs is hard to predict as you have no control of it's logic state.

If it is a TTL chip, then you can assume that both inputs will be threated as logic high, but it may still be a source of error.

 

[crutschow]

yes i know. but they are not combined to any signal so they are zero from the beginning. what happens then?

The output remains in what ever state the FF assumes when the power is applied (which generally is arbitrary and unknown).