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Here a more thorough approach. Note that to realistically display the transit delay, you need to make the clock amplitude a function of Vdd. Furthermore, it is more realistic to drive the gates of the inverter under test with a signal that comes from another similar capacitively-loaded stage; not from an ideal voltage source with near-infinite rise/fall times.
I show how to use the cursors built-into the plot pane to display the delay from 50% on the red V(in) on the upper pane to the red V(out) on the lower pane.
The ultimate inverter delay measurement method is to build a ring-oscillator out of an odd number of inverters, typically 11 to 31 stages, and then just measure the frequency of oscillation.