Hey Len. thanks for the drawing, You're welcome. will try pick up that chip tomorrow. Few questions about the details:
1. I take it because Gs, and E0 are outputs, I can obviously leave them disconnected, or open. Yes. I see pin 7 (I think you mean pin 4) is an input, thus I understand why its connected high, in order to eliminate it activating. Yes. Pins 4, 5 & 10 are inputs and must be defined. What I'm not too sure about is why did you connect pin 16 and 8 together with what looks like a 100nF capacitor? See below.
The rest of the circuit looks very straight forward. I also went through the truth table and checked out all the logic, seems perfect. Good.