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Highly resonant 1Hz circuit?

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Mr RB

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HI, I'm doing some time calibration and measuremnt stuff using a GPS module that puts out 1Hz timepulse, at 50% duty cycle.

The GPS unit makes the 1Hz pulse using a DDS system from it's internal xtal (TCXO) and the result is that the average seconds are perfect (over enough seconds) but any individual second can have a tiny amount of edge jitter caused by the digital timing system inside the GPS module.

It would be handy if I could remove that edge jitter in an analogue circuit and get the filtered average seconds, which I am going to use to discipline another oscillator.

Does anyone have a suggestion for a massively resonant 1Hz circuit? Something that resonates at 1Hz, and is fed from the GPS 1Hz pulse. Ideally it should be resonant to the point that even if the input pulse stops it should still keep resonating at 1Hz for 30 or so seconds.

The idea is that any edge jitter on the incoming 1Hz signal would be insignificant compared tot he average 1Hz resonance.

Thanks! :)
 
What's wrong with a PLL (or variant)?
 
I would have thought that you would reduce the effect of the jitter by filtering the correction signal that you are using to discipline the other oscillator.

I was involved in the design of this GPS disciplined oscillator, where there was quite a lot of digital filtering of the correction signal. As the oscillator being controlled was itself a good ovened oscillator, there was no need for wide ranging corrections. I don't know what type of oscillator you are trying to control, and you might need faster or wider ranging corrections.

There is also a problem with using a 1 Hz resonant circuit. It won't free-run at the correct frequency. If you are exciting a resonant circuit at 1 Hz, it will oscillate at 1 Hz, and the amplitude will depend on the Q of the circuit and its self-resonant frequency. When you cease exciting the circuit, it will oscillate at its self-resonant frequency, and the amplitude will decay at a rate dependent on the Q of the circuit. The frequency during free running will not depend on the previous excitation frequency; it is only the initial phase that was controlled by the excitation frequency.

You could make the 1 Hz oscillator part of a PLL, so you control its frequency, and then it would run at the correct frequency during free-running. However, it would be a lot easier to use a much higher frequency oscillator and a divider in the PLL, which then becomes the GPS discipled oscillator you were making in the first place.
 
I agree that a 1Hz resonant circuit is unlikely to do what you want but I think a PLL will work. Have the PLL generate a 1Hz output from the 1Hz reference (the PLL VCO can operate at a higher frequency with a counter to reduce it to 1Hz). The loop filter, with a suitable time-constant, will remove the cycle to cycle variations. If you want the PLL oscillator to keep on frequency even if the input signal is removed then use a track and hold circuit to hold the loop feedback voltage if the input is lost.
 
A potential problem with a PLL is the phase jitter of the VCO. If it is an RC oscillator, it may have as much jitter as the DDS unit you are trying to improve on. An RC oscillator may also be sensitive to power supply noise, depending on the design.
A low jitter VCO (one with a high-Q resonant element), such as a VCXCO with a frequency divider, would have a better chance of giving you low enough jitter to solve your problem. You could try an RC oscillator with a divider. You might just have to run some tests to see what type of oscillator (and divide ratio) you can get away with.
As Carl suggested, a track and hold (use hold when signal dropout is detected) should give you low drift. You have to pay attention to VCO control voltage ripple. It needs to be very low in front of the T&H, and the T&H has to have very low charge injection (low offset between track and hold modes).
 
Thanks guys for the suggestions. A PLL is more complex and more work than I really wanted. That's my fault, asssuming a "resonant" circuit might be the best way to get that result very simply. :)

How about simplifing the goal to a small simple circuit (an opamp or dual opamp?) acting as a severe low pass filter so that some small edge jitter on the incoming 1Hz signal will be reduced by a factor of at least 10 to 20 times when the 1Hz comes out of the circuit? A 1Hz sine from the output is fine, provided it's >3v p/p.

To Diver300; very nice module you made there! Yes I have considered just removing the 1PPS edge jitter with software, but I wanted to experiment with a number of methods of syncing to and using the 1PPS signal, so I thought it would be nice to have a "filtered" 1PPS signal to start with. This is not really to get a single finished working result, it's more about making a test setup to try some ideas on. :)

Hi Roff, we posted at the same time! I'm not really after being able to continue output when the 1PPS pulse is gone, that was just my clumsy attempt to describe a massive filtering effect. For now I'm after a very simple way to greatly reduce the edge jitter on a signal that is known to be almost exactly 1Hz.
 
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So, something like a high Q active bandpass filter, maybe.
Drift could be a problem. A switched-capacitor filter might work, but it's probably lots more hardware than you want to deal with.
 
Thanks for the suggestions.

Now it looks like there's another problem. With a lot of filtering and a sine output the rate of change is very slow, so my comparator that converts it back to a square wave for digital sampling is now introducing a lot of timing noise on the trigger edge. So it's basically replacing the original <0.1uS edge jitter with a >5uS random edge placement.

At this point it looks like getting a good result from a filter is a bust.
 
A jitter reduction circuit can be made by feeding your jittery square wave into a positive edge triggered monostable multi-vibrator having a jitter-free positive output pulse width. The output of the mono is then precision integrated with an op amp to form a triangle waveform. The negative slope of the triangle waveform will then cross through an arbitrary positive DC threshold at precisely equal intervals, the jitter depending mainly on the jitter on the positive output pulse width of the mono (see attached figure) and the quality of the integrator. A precision comparator detects when the falling slope of the triangle waveform crosses the threshold to generate a pulsed output with reduced jitter on the leading edges. With only 100 nS of jitter on your input pulse, the challenge will be to make a mono with a pulse width that varies from pulse to pulse by significantly less than 100 nS, which should not be difficult. At such a low frequency, the precision and repeatability of the integrator and comparator should not be a challenge.

Credits to (and where you can get more detailed explanation): https://www.electro-tech-online.com/custompdfs/2013/06/EECS-2007-96.pdf
 

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Thanks Ccurtis, that's a really clever system. :) I especially like the way it could be done in software, with the monostable up-ramp being replaced by a fixed time count up, and the down-ramp by a count down with digital setpoint. That would require the jitter to be large compared to the count rate so would be best on low freq signals with high jitter.

But for my application re this thread I don't think it's ideal. The jitter I am trying to remove is generally 50nS per 1S (1 part per 20 million) and the chance of making a monostable with a timed period more precise than that is low, as is the integrator and threshold. Just 5v PSU variance alone is going to be in the 10's of millionths even with a good regulator. By the time it has some type of active precision regulator(s) and precision monostable and threshold it's getting far from the goal of a very simple filter.

I do appreciate you posting it though, it's a great system. For now re this app I designed a math filter algorithm that has very high filtering and zero accumulated error, which has been working well for the clock timing tests I needed to do. If not perfect, at least it was a zero-hardware solution and got me up and running.
 
I know it's getting back to the PLL, but can't you use a PIC with crystal to provide the 1Hz ± 30ppm base frequency (using the hardware CCP/PWM) and adjust that frequency by adjusting the voltage across a varactor/varicap/diode connected to the crystal (using another PWM channel with very heavy filtering to control the reverse bias voltage)? The frequency would be calibrated against the GPS pulse over a number of minutes; if the error is large, i.e. more than a few cycles per period, then the output signal would be brought back in phase and the varicap adjusted immediately for faster initial response.
 
Hi dougy, yeah that's a pretty standard way of doing it. Mainly this is for test purposes, measuring the GPS 1PPS drift. It would have been nice to have the 1PPS pulse jitter free for testing, but as you (and Diver300) said it can be filtered out in software. My issues with that is that I wanted to separate short term jitter error on the 1PPS signal from longer term drift error caused by moving satellites, and both errors are very small.
 
It would have been nice to have the 1PPS pulse jitter free for testing, but as you (and Diver300) said it can be filtered out in software. My issues with that is that I wanted to separate short term jitter error on the 1PPS signal from longer term drift error caused by moving satellites, and both errors are very small.
The method I just described should give you very little jitter (just the jitter inherent in the crystal oscillator and feedthrough from the heavily filtered control signal) and a very accurate frequency.
 
Yep. :) That is what I have done this time with a digital filter.

But the goal was to measure the drift of the GPS (caused by satellite movement), and with all digital filtering it tends to remove both jitter and drift, because they are both very small. I've got a result for now using two separate digital filters (separately tuned) but it would have been nice to have the short term jitter removed by hardware.
 
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