I think that you don't understand me.I need an explanation why
these clocks are non-overlapped? I don't know what device are used (by type number),
I only know that all logic gates are realised in CMOS technology.
So I don't know how to draw signal at the output of first NAND gate,actually why on the diagram
you were posted rise time and fall time (tphl i tplh are diffrent) of signal V1 are diffrent,but
rise time and fall time at the output of the inverter are the same?