# Help me with a Binary Counter , Please .

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#### gooni

##### New Member

Design a binary counter that counts as below:

7-6-5-4-3-2-1 then resets and counts 6-5-4-3-2-1 and then resets and
counts 5-4-3-2-1 and then resets and counts 4-3-2-1 and then resets and
counts 3-2-1 and then resets and counts 2-1 and then resets and counts
7-6-5-4-3-2-1 and so on ......

So the counting sequnce is
7-6-5-...-1 then 6-5-...-1 then 5-4-...-1 then 4-3-...-1 then 3-2-1 then
2-1 then 7-6-5-...-1 then 6-5-...-1 and so on.

Note : We are only allowed to use T,R-S,J-K flip flops and standars gates such as OR,AND,XNOR,XOR,NOR,NAND,Not and ....

TA .

#### MrAl

##### Well-Known Member
Hi,

Here's a rough idea how to start...

Build two counters, not one. One counter does the actual counting,
the second counter counts the number of times the first counter got
to zero (which also resets that first counter too).
The second counter is used to 'preset' the first counter, so that each
time it is preset it gets preset to a lower count.

You'll need the flip flops to build the counters, and the regular gates to
detect the count to zero for the first counter and the count to 1 (or 2)
for the second counter.

#### lord loh.

##### Member
That is roughly correct...

1. UP Down Counter
2. Counter2
3. JK Flip Flop that is toggled when the UP- Down counter is reset or reaches 0. This bit is used to count either in up / down direction.
4. cause the up - down counter to reset when up - down reaches the value of the Counter2. Decrement counter2.

I think that is about it... You can build a comparator using those gates.

Hi Again

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• My Design 001.jpg
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#### gooni

##### New Member
I couldnt catch you:
"The Up-Down counting logic is missing."

Lets check it out:

We have a main counter which is an Asynchronous Down Counter.
It starts counting : 7-6-5-..-2-1.
When it reaches 1 , the NAND gate decodes "1" and so sends this "1" to the
Second Counter as Clock Pulse (CP).

The Second Counter (which is an Asynchronous Down Counter also) counts 1 step down (here 110=6).
This "110=6" resets the Main Counter to "110=6".
Now the Main Counter counts : 6-5-4-3-2-1.

When it reaches "1" again , the NAND gate decodes "1" and so sends this "1" to the Second Counter as Clock Pulse (CP) again.

The Second Counter counts 1 step down (now 101=5).
This "101=5" resets the Main Counter to "101=5".
Now the Main Counter counts : 5-4-3-2-1.

This procesure will continue ....

Im alittle bit in doubt.
Any Idea?

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#### Wond3rboy

##### Member
These are the potential problems that i think will appear(since i dont think you have simulated your ckt).

1) The main counter is NOT a asynchronous DOWN counter. These are the connections of a asynchronous down counter.

2) As far as i know if RD and/or SD are kept in thier active state, the counter wont count and the clock pulses will have no effect.So if you keep the preset value on the Main counter then it will not count.

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#### Wond3rboy

##### Member
Although i dont understand the updown logic.Here is a very simple approach to making your counter go up or down. It requires 8 Nand gates for every output.

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• 07062009158.jpg
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#### lord loh.

##### Member
To Gooni:

Sorry I was under the impression that the counting was 7-6-5-4-3-2-1-2-3-4-5-6-5-4-3-2-1-2-3-4-5-4-3-2-1....

#### gooni

##### New Member
Dear lord loh.

Is there something wrong with it?

#### lord loh.

##### Member
Wond3rboy is right about his second point.

Once counters 1-2-3 reach 001, it shall give counter 4-5-6 a pulse which shall cause output Q4 or register 4 to go from 1 to 0 (or 0 to 1. I am specifying a case (1->0) when your counter shall get stuck).

The output Q4 shall reset Register1. And it shall be in reset sate unless the Rd1 is made high again. What makes Rd1 high? Counter 1-2-3 being 1... Which shall never happen as Counter 1 is stuck at 0.

This is a deal lock condition.

#### ljcox

##### Well-Known Member
You're on the right track.
You need to add gating to set the Main Counter (MC) according to the state of the Second counter (SC).

The will require twelve 2 input NAND gates going from the Q and Q bar outputs of the SC to the Sd and Rd inputs of the MC.

When MC = 0, you set MC = SC.

When MC & SC = 0, I suggest that you then set SC to 7 and then (after a short delay) preset the MC to the state of SC, ie. MC = SC = 7.

You will also need a reset button to set the counters to 7 when the power is turned on.

Alternatively, you could use a "Reset on Power on" circuit.

Either way, you simply set the SC to 7 and make MC = SC as I said above.

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#### ljcox

##### Well-Known Member
I edited my previous post to correct an error and the add extra info.

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