Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.
Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.
I'm having difficulties troubleshooting a possible unintended latch. The board I'm testing with is an Altera DE2-115. I'm using the platform designer and the VHDL code that I had to enter was just the component and ports:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all...
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