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Flip-Flop Counters Starting at "N" continuing to "X"

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At first, I mastered how to make flip-flops that start at zero and end at the last digit.
Then, I learned how to start at zero, and then end at a digit before the final number.
Finally, I was excited when I figured out how to make it count down... From the final number to zero.

Unfortunately, I have no idea how to start the number at "N" and end at "Y" (where "N" is a number after zero and "Y" is a number before the final number) and count down from "Y" to "N".

For example, I played with a mod-7 counter for around an hour to try and get it to start at two and end at 5. I got the counter to start at two, go to three, and then stay there for the rest of the day...

Failure at its finest, please help me.
I have a final coming up soon and even my teacher doesn't seem to understand this :-(
 
Did anybody teach you to draw a "state-transition-diagram"? How about a "present-state, next-state" table?
 
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Did anybody teach you to draw a "state-transition-diagram"? How about a "present-state, next-state" table?

Well, I don't exactly know what you mean by that...
Maybe I have, maybe I haven't.

P.S. I got the flip flops to count from one (1) to "X"! Sadly, I can't get the two (2) to work...
 
The reason you are struggling is because it's not a simple thing to do. You need decode logic to sense when the count has reached it's maximum, and reset logic that will start the count at the desired minimum value.

If, for example, you want a counter to count up to 5, then you must decode the binary 5 at the counter's output. Hence,

startover = q0 AND NOT q1 AND q2 AND NOT q3...

q0 -----|\___________|\_______start over
q2 -----|/...........____|/
.......................|
q1---|>o|\_____|
q3---|>o|/

|\ *note: these symbols are AND gates
|/

*note: ignor the periods in these diagrams. This is the only way I can get the logic diagram to space correctly.


Then, the signal "start over" has to generate the desired starting value: ie if you want to start at 2.

start over--|-----|>o---|-----d0
................|------------)-----d1
..................................|-----d2
..................................|-----d3

where |>o is an inverter
 
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Of course, the first diagram can be simplified, since the counter won't go past binary "101", the output q3 can safely be ignored. It's up to you to find wats to simplify it further.
 
...
P.S. I got the flip flops to count from one (1) to "X"! Sadly, I can't get the two (2) to work...

Your initial post was ambiguous. Do you want a counter that counts: 2,3,4,5,2,3,4,5,2...

If so, I can do it with only two D flip-flops and one gate. It has no false cycles or hazards. It can be reset asynchronously to state "2".
 
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Your initial post was ambiguous. Do you want a counter that counts: 2,3,4,5,2,3,4,5,2...

If so, I can do it with only two D flip-flops and one gate. It has no false cycles or hazards. It can be reset asynchronously to state "2".

Let's see...
Just to make it all simple, I want a counter that goes from two to 15.

This meaning:
2, 3, 4, 5, 6, 7, 8, 9, A, b, C, d, E, F, 2, 3, 4, 5, ...

I've attached my mod-16 counter (it does work).
For convenience sake, flip flop one's output is Q1, flip flop two's output is Q2, etc.
I can only use a NAND to do the preset/clear functions (as in take the outputs of the flip flops and use then in determining when the flip flop will be cleared/reset).

Look at the second attachment for my six to two down-counter for an example of what I mean by only using a NAND.
 

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Well for starters, you're using asynchronous pins Preset/Clear to "preset" your counter each time you roll to the start. The problem with that is that you never reach your desired count, because just as soon as you decode it, the counter re-initializes to the beginning. You need to use the J&K pins to 'set' the beginning count, and then work out the details of how to connect the detector to get that value on the next clock. For example, if you wanted to start at a binary two (0010) then you would connect the NAND gate output to the k-pin on q0, q2 and q3, and to the j-pin at q1. However, when you're not decoding the max count, ie when you're just counting up, you'll have to have those pins connect normally, when means you'll have to multiplex the decoder ( the NAND gate's output ) to the j&k pins. This will complicate the design, as you'll need at least 3 gates for each flop to reset the count. You'll also need more than just NAND gates.

If there is an easier way, then i don't know what it is. This is the only method that will yield reliable results for different count patterns. You just have to bite the bullet and deal with the complexity.
 
Your method of decoding the final value and then applying that signal to the asynchronous Set and Clear inputs is unreliable, especially considering the underlying counter is a Ripple counter. It may work at one supply voltage but not at another. It depends on the propagation delay of specific parts; if you build the circuit a dozen times, some may work and others wont because the propagation delays of the parts change. This is not the way to build counters.

The correct way is to build this is as a synchronous counter, where all FFs are clocked at the same time by the same Clock edge. The gating for the J and K or D inputs of all four FFs will be uniquely determines by each desisired state transition. This is done by writing out a present-state/next state table for all fourteen desired state transitions.
 
Lying in bed last night, I suddenly remembered how J-K flipflops work. I had forgotten their state depends on their previous state. The important equations to remember are:

Q=~Q and J or Q and ~K
~Q=~Q and K or Q and ~J

where ~ = "NOT"

With that, there is a simplification that can be used here when rolling the count from "1111" to "0010", and that is to just connect the output of the NAND gate to k1. In fact, just connect it directly without additional logic.
 
Your method of decoding the final value and then applying that signal to the asynchronous Set and Clear inputs is unreliable, especially considering the underlying counter is a Ripple counter. It may work at one supply voltage but not at another. It depends on the propagation delay of specific parts; if you build the circuit a dozen times, some may work and others wont because the propagation delays of the parts change. This is not the way to build counters.

The correct way is to build this is as a synchronous counter, where all FFs are clocked at the same time by the same Clock edge. The gating for the J and K or D inputs of all four FFs will be uniquely determines by each desisired state transition. This is done by writing out a present-state/next state table for all fourteen desired state transitions.

Yes, keep in mind that there are more ways than one to do this. I encourage you to keep experimenting and learning how these counters work, and to eventually try to build one as MikeMi is suggesting here. You could start by connecting the clock directly to the clock input of each flop, then connecting each j&k to the q and ~q outputs of the preceeding flop, ie

J(n) = Q(n-1)
K(n) = ~Q(n-1)

Then look up state transition diragrams, keeping in mind the formula for q and ~q that I previously posted. If you need help understanding the diagrams, then ask... we can help with that too.

Good luck!
 
Finals went well

Hey all!

Took my finals a while back. I actually managed to check my mail and find that you all had replied one day before the finals and looked at the various comments.

Looks like your advice helped and I apparently got a 98 (highest in the class). The two points I lost were because of stupid mistakes (but those are the easiest to fix!). I thank you all for helping me and wish all of you a happy life. I'll be sure to come back here again when I have more electrical issues.

:D
A satisfied human being,
-Terms
 
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