FET driver IC question

[Chris Wilson]

Would you expect the gate drive voltage level of a FET driver IC to rise and fall under drive load with the chip's Vcc?

Thanks.

 

[MikeMl]

Which gate driver IC?

 

[Chris Wilson]

Which gate driver IC?

I see this with both an MCP1404 and an IR2110

https://www.farnell.com/datasheets/...MI2d324tS72AIVlB4bCh0GEgL8EAQYAiABEgLzkfD_BwE (MCP1404)

**broken link removed** (IR2110)

The IR2110 has both a 5V and a 12V supply. The 5V is through a separate regulator off the 12V supply, so it's not the 5v supply that I am adjusting.

Thanks!


On the MCP1404 the gate (and drain) waveforms go to pot much over 10V and to a lesser extent under 7V. At 9V all looks well, but I am not sure this should be occurring....? They are driving a push pull Class D amp at 136kHz using a pair of FQA34N20L in parallel each side on a 52V supply (about 1kW)

 

[kubeek]

Eh? A schematic of what you´re measuring and what you´re changing, please.

 

[Chris Wilson]

Eh? A schematic of what you´re measuring and what you´re changing, please.

2 schematics hopefully attached, one using IR2110 and the other using MCP1404 thanks kubeek.

 

[dknguyen]

2 schematics hopefully attached, one using IR2110 and the other using MCP1404 thanks kubeek.

If the Vcc is the voltage being used to drive the gates, so if Vcc changes, the gate drive voltage will change. So if you connect Vcc to 12V, of course your gate drive voltage will be over 10V. But the FQA34N20L gate can handle up to 20V though, so why do you care?

Keep in mind that the high-side gates aren't driven directly from Vcc. They are driven from floating bootstrap capacitors that are periodically charged with Vcc, and while they are floating and driving the gate, their voltage will decrease. So some voltage headroom is healthy in order to prevent the caps from discharging to a voltage that is too low.

On the MCP1404 the gate (and drain) waveforms go to pot much over 10V and to a lesser extent under 7V. At 9V all looks well, but I am not sure this should be occurring....? They are driving a push pull Class D amp at 136kHz using a pair of FQA34N20L in parallel each side on a 52V supply (about 1kW)

I think there are some typos here so I'm not sure what you are trying to say, but if I had to guess, I am thinking you are asking if it's normal for the gate drive voltage to start out high, and slowly decrease every time the gate is turned on. Yes, this is normal for the gates driven by the high-side output only because they are driven from floating bootstrap capacitors (described in the first half of my post). This is not normal for the low-side outputs since they are driven directly from Vcc.

 

[Chris Wilson]

If the Vcc is changing, yes, the gate drive voltage will change. Vcc is what is being used. Your FQA34N20L gate can handle up to 20V though so why do you care?


I think there are some typos here so I'm not sure what you are trying to say.

When I talk of 10V, 7V and 9V this is Vcc on the driver IC. Let's say at 10V or more Vcc on the IC type MCP1404, then the gate voltage on the scope is still WAY below 20V, but the gate waveform is going haywire. At 9V it's fine, below 7V and it starts to fall apart again. I had (wrongly) assumed a FET driver chip would give a constant gate voltage output within a reasonable range of its Vcc level. Thanks for the replies

 

[dknguyen]

Actually, what I said is only true for the IR2110s. Your schematics are all funky and seem to be missing parts required for the IR2110 I don't know what's going on (I see no bootstrap caps or diodes in the schematic you provided. You can see what they look like in the part datasheet on page 1: it's the diode and the cap between Vs and Bs) , but in the way the IR2110 is used, what I said is true.

The MCP1404 does not seem to allow for high-side gate drive (no provisions for a boostrap diode or capacitor) so I don't know why you are seeing falling gate voltages with this one.

But yeah, if your desired gate drive voltage is 10V, you want to drive it from something like 12V, or even 15V (maybe even higher as long as it's within the tolerance of the gate) if it's being driven from a bootstrap cap supply so it doesn't dip too low.

EDIT: I think I see why your schematic seems to be missing components and is funky to me. A push-pull circuit doesn't have any gates that have a floating sources so they don't need the boostrap supplies which is why I see no bootstrap caps or diodes. The MCP1404 was never able to provide this floating gate drive so it was just used as is while the IR2110s just had it's high-side supply pins fed directly to 12V rather than through a bootstrap cap and diode since the floating gate drive was not needed.

In which case, I'm not sure why you have voltage sag. Can you please post a picture of your waveform? It's your gate voltage that is sagging right? Not Vcc itself? And are you measuring the voltage at the MOSFET gate? or at the driver IC pin?

 

[dknguyen]

I suspect what's happening is the AC coupling capacitors on the inputs to your driver ICs are charging up the longer the gate is on for which causes the input to slowly approach ground the longer it is on for which slowly turns off your FETs. Do you need to AC couple these inputs? What happens if you just short across them? If you just apply a direct 3.3V or 5V to these inputs you should see no voltage sag on the gate while it is on.

You can verify this by scoping the voltage at the input to the IC.

 

[Chris Wilson]

OK, let me post three scope captures. Bottom traces are gate voltage waveforms at the actual FET gate pin. X10 probes.

Upper traces are drain waveforms at the drain pin itself of the FET.

File names should be self explanatory, but basically the three waveforms are at 9V (works great), 6.8V (waveforms noisy) and 11.7V (waveforms have gone to pot, only saving grace is current limiting on the supply stopping cross conductance blowing a FET) the 9V, 6.8V and 11.7V are measured at pin 6 of the MCP1404 and it comes from a quality linear regulated bench supply and has good decoupling at the pin 6 of the IC itself.

 

[Chris Wilson]

I suspect what's happening is the AC coupling capacitors on the inputs to your driver ICs are charging up the longer the gate is on for which causes the input to slowly approach ground the longer it is on for which slowly turns off your FETs. Do you need to AC couple these inputs? What happens if you just short across them? If you just apply a direct 3.3V or 5V to these inputs you should see no voltage sag on the gate while it is on.

You can verify this by scoping the voltage at the input to the IC.

Ok, my worry is these caps are there to stop any chance of a FET being held on if the CLK0 or CLK1 outputs of the Si5351A synthesizer are held high. I need to check this. What is the point of all this you may ask? Well, I am trying to learn and the designer of the exciter for this amp, a gizmo called a U3S by QRP Labs has issued a new firmware that allows one to have 180 degree inverted outputs from CLK0 and CLK1 of the Si5351A chip. This would allow me to simplify the amp and get rid of the 74F74 flip flop, which needs a X2 frequency from the U3S as it halves the frequency as it divides the phase. My issues have been this varying Vcc voltage effect on the gate drive voltage, and getting enough swing from the Si5351A synthesizer chip to drive the IR2110 properly. The MCP1404 seems happy with less swing.

Finally, I have concerns as to whether there is any inbuilt "dead time" on an MCP1404? I know there is on the IR2110 but that seems to want more drive than the Si5351A can provide. I am at the extreme of my comfort zone here, but love fiddling and would like to simplify this as much as possible. Thank you very much for your help here, it's much appreciated!

 

[alec_t]

I note you have no connection to pin 5 of the IR2110. With your circuit configuration you may need to ground pin 5 to get consistent results.
C1 and C2 will drive pins 10 and 12 negative, beyond their allowable limit (Vss-0.3). That may lead to malfunction of the IC.

Edit:
My reading of the IR2110 datasheet is that the output stage is "designed for minimum driver cross-conduction". Any dead-time that involves will be minimal. I see no mention of dead-time and assume it is up to the user to provide that, by suitable timing of the Hin and Lin signals.

 

[dknguyen]

Let me try and get this thread back on track. Let's start from the beginning with just the reference materials provided and your actual question.

If you forget everything I have said in this thread so far, and provided me with only the question in first post, part numbers, schematics, traces, my answer would have been:

"Yes. Vcc is what is being used to drive the gate voltage so if you change Vcc, then gate drive voltage will also change. That is what you see in the lower traces."

However, this question seems to not have been your original concern. Either, it arose because you mistakenly attributed it to your original concern because everything else or you flubbed up your wording somewhere. If we start, from the beginning, with no text, and only schematics and traces, what is your question? Let's start from the beginning with just the reference materials provided and your actual question.

Alternatively, join me in the chat. I'll be waiting here.

 

[Chris Wilson]

Hi again, not sure how to operate the chat function, sorry. My question, just given the traces, would be why do the gate waveforms go nasty when Vcc is raised or lowered, yet the gate voltages seem within spec range of the FET's?


I have just been doing some more testing and I believe I have found a firmware glitch in so far as CLK1 has a high frequency signal on it after a TX session has ended, and I believe there shouldn't be *ANY* signal on it, so I need to bring this to the developers attention. I don't think it will cause an issue as it's very low amplitude, but it shouldn't be there.

 

[dknguyen]

Hi again, not sure how to operate the chat function, sorry. My question, just given the traces, would be why do the gate waveforms go nasty when Vcc is raised or lowered, yet the gate voltages seem within spec range of the FET's?

There is the issue in communication. The gate waveforms are the lower traces. The drain waveforms are the upper traces that you are asking about which are going nasty. I'll get back to you later but it's probably parasitics causing the ringing though I'm not sure why they would get worse at lower voltages rather than just higher voltages (with higher voltage not . Chat button is a button in the top bar.

 

[dknguyen]

Oh, you do realize the IR2110 has an undervoltage lockout right? Your FETs might be able to run off a gate voltage of 5V, but that doesn't mean the driver is designed to drive at that low a voltage. Are you implying that the traces for the IR2110 look similar to those you provided for the MCP1404? If so, I'm surprised it worked at all at 6V and 9V since the driver should have locked you out.

The MCP1404 works between 4.5v and 18V.

 

[alec_t]

Going back to your post #1 question; yes, if Vcc is changed then the gate drive voltage will change by approximately the same amount, for either IC. In the case of the IR2110, though, Vcc must stay above 10V to prevent the under-voltage lockout acting.

 

[ronsimpson]

if Vcc is changed then the gate drive voltage will change by approximately the same amount

Looking at the schematics and scope pictures, I think the 12V has serious ripple on it. Caused by a lack of capacitors on the 12V at the IC. There needs to be a 0.01 to 0.1uF cap at the IC and about 100uF high current cap some where near the IC.

This looks like a RF project, where two feet of wire going to a supply will act like an inductor. Some wire and a 0.1uF cap can resonate at the transmitting frequency and cause strange problems.

 

[ronsimpson]

I think the 12V supply has a sign wave on it.

 

[kubeek]

I think the 12V supply has a sign wave on it.View attachment 110011

Quite possibly, but it would be a sine wave, not a sign wave