Which gate driver IC?
If the Vcc is the voltage being used to drive the gates, so if Vcc changes, the gate drive voltage will change. So if you connect Vcc to 12V, of course your gate drive voltage will be over 10V. But the FQA34N20L gate can handle up to 20V though, so why do you care?2 schematics hopefully attached, one using IR2110 and the other using MCP1404 thanks kubeek.
I think there are some typos here so I'm not sure what you are trying to say, but if I had to guess, I am thinking you are asking if it's normal for the gate drive voltage to start out high, and slowly decrease every time the gate is turned on. Yes, this is normal for the gates driven by the high-side output only because they are driven from floating bootstrap capacitors (described in the first half of my post). This is not normal for the low-side outputs since they are driven directly from Vcc.On the MCP1404 the gate (and drain) waveforms go to pot much over 10V and to a lesser extent under 7V. At 9V all looks well, but I am not sure this should be occurring....? They are driving a push pull Class D amp at 136kHz using a pair of FQA34N20L in parallel each side on a 52V supply (about 1kW)
If the Vcc is changing, yes, the gate drive voltage will change. Vcc is what is being used. Your FQA34N20L gate can handle up to 20V though so why do you care?
I think there are some typos here so I'm not sure what you are trying to say.
Ok, my worry is these caps are there to stop any chance of a FET being held on if the CLK0 or CLK1 outputs of the Si5351A synthesizer are held high. I need to check this. What is the point of all this you may ask? Well, I am trying to learn and the designer of the exciter for this amp, a gizmo called a U3S by QRP Labs has issued a new firmware that allows one to have 180 degree inverted outputs from CLK0 and CLK1 of the Si5351A chip. This would allow me to simplify the amp and get rid of the 74F74 flip flop, which needs a X2 frequency from the U3S as it halves the frequency as it divides the phase. My issues have been this varying Vcc voltage effect on the gate drive voltage, and getting enough swing from the Si5351A synthesizer chip to drive the IR2110 properly. The MCP1404 seems happy with less swing.I suspect what's happening is the AC coupling capacitors on the inputs to your driver ICs are charging up the longer the gate is on for which causes the input to slowly approach ground the longer it is on for which slowly turns off your FETs. Do you need to AC couple these inputs? What happens if you just short across them? If you just apply a direct 3.3V or 5V to these inputs you should see no voltage sag on the gate while it is on.
You can verify this by scoping the voltage at the input to the IC.
There is the issue in communication. The gate waveforms are the lower traces. The drain waveforms are the upper traces that you are asking about which are going nasty. I'll get back to you later but it's probably parasitics causing the ringing though I'm not sure why they would get worse at lower voltages rather than just higher voltages (with higher voltage not . Chat button is a button in the top bar.Hi again, not sure how to operate the chat function, sorry. My question, just given the traces, would be why do the gate waveforms go nasty when Vcc is raised or lowered, yet the gate voltages seem within spec range of the FET's?
Looking at the schematics and scope pictures, I think the 12V has serious ripple on it. Caused by a lack of capacitors on the 12V at the IC. There needs to be a 0.01 to 0.1uF cap at the IC and about 100uF high current cap some where near the IC.if Vcc is changed then the gate drive voltage will change by approximately the same amount