Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.
Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.
I checked his account and he has not used it for a few weeks now.
That's a good idea though, so do you know any other way to contact him or someone else who might be able to answer this at ARM?
I ended up starting a technical case for this issue with ARM.
In the mean time, i found the spec for another device that is used on many displays, the PCF8574 which is an I2C to parallel interface chip.
To contrast, the input protection diodes on the PIC 12F675 for example have a rating of 20ma (upper or lower), while the 8674 chip has a rating of 400ua, which represents a difference of 50 to 1.
This i believe illustrates the genuine need for this kind of detailed information, and sometimes not just on a per-chip basis, but sometimes on a per-pin basis. The ARM chip i believe could have a per-pin rating because of the additional variability of the output drivers used internally.
I "suppose" there is no real ESD protection. Why? The ESD protection design is based on the external world interface, not chip based. See: **broken link removed**
The "inherent" substrate diodes are something else entirely. The ones rated for Vcc+0.3V and Gnd-0.3 V or so. They can't be considered ESD protection.
Where are you getting this information from, such as the diodes cant be considered protection?
Normally the diodes act to shunt current in the event that there is an ESD strike, which would quickly damage the device. There is a limit to the effectiveness, and that is usually measured by the max current specification.
But that's not the only real world use of the diodes. They are typically used to shunt current in the event of a more normal over voltage, such as when the input (to the network) goes above 5v (on a 5v system). For example, on an analog input we might have a 1k series resistor, so that when the input goes to any level above maybe 5.3v such as 6.0v, the upper diode starts to conduct, and so the current is shunted to the +5v supply rather than allowing the pin voltage to go all the way up to 6.0v. The current rating for that diode is limited however, and that sets our 'protection' scheme limitation specification. For that same example with a 1k series resistor and assuming conduction starts at 0.3v above 5v and assuming the current rating of the diode is 10ma, we have:
0.010=(Vin-5.3)/1000
and solving for Vin we get:
Vin=10+5.3=15.3v
So if our analog input to the circuit goes above 15.3v the current will exceed the diode rating and therefore fuse the diode. There's a time factor too, but this keeps it simple.
This means we dont need an external diode, or at least we have a way to determine if our circuit is going to survive based on what we know about the expected range of possible input voltage from the real world application.
An application might typically be set up to measure voltages from 0 to 20v, with the appropriate resistor divider. The impedance of that divider limits the over voltage that the system will tolerate such as 30v, 40v, 50v, etc., even though the measurement limit is 20v based on the ADC unit bit size itself.
So the key point is, knowing the specification of these diodes allows us to know if and when we need more protection than the chip can offer all by itself. For many applications we wont need any more protection so it is silly to introduce such a thing, but in other applications we will end up blowing out the chip if we dont take extra steps to either add more protection directly, or alter the design to make it more tolerant (such as increasing the impedance of the external resistor network in the example above).
So you see how easy this should be, and it is, when the spec's are given. When the spec's are not given, we have no way of knowing what the impedance should be or anything else like that.
My understanding is that the Shotkey diodes are "just there" because of the IC manufacturing process. I think you have a metal/semiconductor which gives you a shotkey diode. The metal is the substrate and you have a semiconductor on top of it. I think I'm going from memory from by solid state physics courses. They are not tailored with specific characteristics. The just "have" some typical characteristics which may be known.
Well, this is like i am asking how fast a particular model car can go and you are telling me that "cars have engines".
So i am not sure what you are trying to say here.
We might be able to glean some little information from thinking about the substrate diode however, in that it must come from the same sub micron process that the internal mos transistor was build from and have the same physical area. This could point to the following conclusions:
1. A pin that can source 3ma will have a diode that is rated for 3ma from i/o pin to +Vcc (3.3v in this case).
2. A pin that can sink 6ma will have a diode that is rated for 6ma from i/o pin to ground.
That could be true because the drain area could be a different size and so the diode it forms with the body will have one part of the junction of the same area, and same for the source. If the transistor can handle 5ma, then the diode must be able to handle 5ma, but no more.
But this still goes without the manufacturers validation. It does seem to make sense though.
Experts in the field of ESD R&D for Arm might take exception . The characteristics of Schottky diodes in a CMOS process are all by design. THe characteristics are critical to performance , and the geometry has improved over recent years with interdigital shapes to reduce ESR and have the equivalent circuit of a chain of parallel diodes with series resitance in series and between each diode. The doping of N wells and deposition of pads are by design and made by routine CMOS manufacturing processes.
But true , they do not have the negative resistance SCR effect of a DS9502. These are popular for EXTRA ESD protection on memory chips ( which humans like to toss around as if they were potato chips.)
First, on contacting ARM, they state that they simply dont know and that you'd have to contact Atmel.
On contacting Atmel, they state:
"Unfortunately we never provide ESD details of the device. We can consider at least ESD protection is up to 2kV for this product."
So in other words they are making micky mouse products. There is no way to properly calculate how well a given pin will hold up under certain abnormal operating conditions, something that is COMPLETELY SIMPLE AND TAKES ABOUT 10 SECONDS using a PIC type microcontroller chip.
I've spend days on this ridiculous problem now, when with the PIC chip i spent maybe 10 minutes the first time the problem presented itself to me. I feel like applying 5000vdc to each pin of every Atmel device i own just to get rid of the dang things now.
All i can say is, if this particular chip blows i'll never buy another one and never condone anyone else buying one either.
There's a small blurb here https://en.wikipedia.org/wiki/Human-body_model concerning testing. 2,4,6 and 8 kV is common. 1500 ohms is the discharge resistor. A 100 pf cap is charged to the test voltage and discharged through 1500 ohms.
It's not a continuous thing. Then there's some stuff about how the testing is done, but I'll bey you have to purchase the standard.
I still think it's best to use ESD protection designed for the "exposed" interface.
We used to use Swiss made Shaeffer ESD guns 30 zaps per unit. back in the day when LEDs were exposed on keyboards,, they would arc thru the slot and fail.
Then in production we had large mainframe IO cables to DISK cabinets on the floor that would zap the drivers from ESD cable capacitance. SO we had to modify the test process.
Our ESD gun had the HUman "middle" finger model and the moving cart model . Another Eng said he used a repetitve sampling O-scope to see 50 picosecond rise times.
THe probability that ARM Cortex chips have no ESD protection is near zero. But if you have IO cables. Plan on TVS chips for all IO pins.
Thanks much guys for trying to help. This turned out to be a very strange problem.
First, do i think they have such a great product that they dont want to reveal the inner workings? I have to say that i can not agree with that because most companies that have a great product want to show it off, so i dont see any benefit from not telling anyone they have the best ESD protection on the earth. I have to assume you were joking
Could i be wrong? Yes, but i would see that as a strong selling point so i cant see why they would not tell anyone.
Let me restate the simpler problem...
Say we want to use one of the analog inputs. Say the analog reference is 3.3v, so that gives us a range of 0 to 3.3v for the analog input. If we go over 3.3v, the upper ESD "diode" will start to conduct at some point and thus shunting the current to the +3.3v supply. If this is a significant current, the +3.3v supply may actually see a small blip that raises that voltage by a small amount like 0.001v, taking it to 3.301v for example. It could be higher than that though, depending on the total impedance load with is the core itself along with any peripherals connected to the +3.3v supply.
But we dont worry about the +3.3v blip for now, we just have to make sure that upper diode doesnt blow out when there is an over voltage on the network that makes up the ADC external circuit.
Now say the ADC external circuit only has to measure from 0 to 3.3v, and may have a 5v over voltage. Since the range is the same as the ADC, 0 to 3.3 v, we dont need a voltage divider, but to protect the internal diode we do need a series resistor, and although that raises the acquisition time a little at least we are protecting the diode.
So the question then is, what size resistor do we use?
With many of the PIC chips, the rating for each diode is 20ma max. So lets say we cut that in half to be safe, and design for a max of 10ma. We end up with the formula:
R=(V1-V2)/I
so for this problem:
R=(5-3.3)/0.01
so:
R=1.7/0.01
R=170 ohms.
and if we wanted to protect against buss contention with this resistor we would need:
R=5/0.01
so:
R=500 ohms.
So in both cases we were able to calculate a reasonable value for the external series resistor, and it took less than about 120 seconds to even type this all out.
Now on to the Atmel chips...
First problem with the over voltage:
R=(5-3.3)/I
so:
R=1.7/?
so:
R=?
and second problem with the buss contention:
R=5/I
so:
R=5/?
so:
R=?
Because we dont know the current rating, we have no way to determine the required external resistor.
Also, the human body model is hard to relate to a constant value for the current. We dont really know the diode area and physical stuff like that which would help figure out the thermal properties of the diode and maybe allow us to calculate an equivalent constant current.
Maybe they are partners with a company that makes external ESD protection devices, so that they can help sales for that second company.
I checked his account and he has not used it for a few weeks now.
That's a good idea though, so do you know any other way to contact him or someone else who might be able to answer this at ARM?
I found another email at his University job thru google
I think using the 3.3 Vcc for the ADC Vref is a weakness
The TI datasheet for the AM3359 [ https://www.ti.com/lit/ds/symlink/am3359.pdf ] recommends 1.8V for the ADC circuit. The max is 2.1.
I don't think I'd recommend using 3.3 for VREFP.
Ok sure, i'll look into that more when i get to that point. I got stuck on this ESD diode issue
I think i found another way now, for what it is worth.
What i was originally thinking was to use a (approximately) 3.000v power supply, shunt regulator, with a diode to the pin, to shunt the upper end voltage in case of over voltage. That's probably the way i will tackle this for the analog inputs. But for the digital i/o that have to interface with +5v, another way might be to place a diode in series with the pin cathode to the pin anode to the 5v system i/o, then another diode to +3.3v, and a pullup on the 5v system input to +5v. This way the 3.3v i/o can pull down the 5v input and allow it to be pulled up on a high output signal, and still be clamped somewhat to +3.3v. This is if the 5v system does not have to put out a low impedance high, just a low impedance logic low. Another diode in anti parallel with the first diode allows the 5v system to pull down the 3.3v i/o acting as input. This could work for some I2C devices i think without too much risk of damage. A small series resistor just in case also. This should work in systems that have an active low but non active (open drain) output, and this is how I2c works too i think.
I wonder how long the lines (reactive noise ingress) are between IO lines and what the power sequence controls are? Otherwise 3.3V could end up powering up the 5V line if high impedance up to a certain voltage thru the 3.3Voh to 330R to Schottky diode to internal diode in 5V logic input.
I suppose that could happen. Whether or not it is a problem would have to be tested. The 330 ohm value is not set in stone either, as the pullup can probably be increased to say 20k then the 330 ohm increased to 620 ohms for example.
I was shooting for a passive-only network, if it works. I know some people are really cutting this down to just a 330 ohm resistor in series with their 1602 LCD display IC2 port !
The analog input ports will still present a more complicated problem however. Leakage from protection diodes becomes an issue.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
