The purpose of internal ESD-protection diodes is self explanatory and logarithmic in nature, but can be linearized for static DC in your example using the incremental resistance or ESR as I call it. I know that the ESR is inverse to the rated steady state power of all diodes. In this case it is a very fast low capacitance diode, much faster than the devices to clamp very fast , transmission line pulses (VF-TLP), it must be limited in steady state power.
to limit the current between 5.5V and 3V using a 10% worst case tolerance difference of 2.5V across a Schottky diode which has a 0.15V threshold and an incremental resistance or ESR at rated power on the order of 15mW but a much higher J rating in the SOA limits of the diode. The trick is that the protection diode must clamp faster than the embedded PNPN SCR effect can respond at 0.65V even though the voltage may in fact greatly exceed 0.7V for many nanoseconds with a 4kV VF-TLP. This is due to the impedance ratio at TLP speeds of the diode vs the substrate capacitance of the PNPN junction in CMOS, which is largely undocumented.
Therefore I would suggest to use 15 mW for the internal CMOS ESD diodes and 1/15mW= ESR of 66 Ohms for the series resistance for DC from the external %V source. THus 2.5V worst case drop into 0.3V the absolute maximum of the CMOS specs is 2.2V difference with 15mW/0.3V= 50mA as the absolute maximum for DC. Therefore the protection R you may use for 5.0V*110% to 3.3V*90% +0.3Vd clipping must be greater than (5.5-3.3V)/50mA=44 Ohms. I would suggest 50 ~100 minimum, unless a lot of lines are interfaced this way with Pd accumulation)
I accept there is no documentation from ARM on the ESD protection diodes and only that it satisfies the IEC ESD standard.
My conclusions above are solely based on my experience with all diodes that seem to follow the incremental ESR <= 1/ Pd where Pd is the static power rating of any diode at 85'C. I have found this to be true from 0.5/Pd ~ 1/Pd for every diode VI curve I have analyzed from LED's to 1000A power diodes. THis also explains all the variations of Vf tolerances for all single LED's ( not strings or arrays of LEDs, where equivalent network ESR must be computed)
I also know that all ARM CMOS devices use ALVC2 type CMOS drivers for outputs with 25 Ohm ESR as opposed to LV CMOS drivers with 50 Ohms and HCMOS drivers with 200~300 OHm ESR driver impedance, so I expect the protection diodes to be as low as possible without compromising the input capacitance and speed if the logic level interface.
You may get a completely different response from ARM tech support, but I have found my experience tells me what I have written.
For more info on ESD protection, but not what you are looking for ....
https://www.google.ca/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0CB0QFjAAahUKEwjLzoOMmfLIAhXFkx4KHRj4B3E&url=https://www.infineon.com/dgdl/AN210_v1_3.pdf?fileId=db3a30432cd42ee3012cee8d005b0c19&usg=AFQjCNFfDCGdtd5FuhIYx2zM7xOO8LgStg&sig2=S_MnkmSnGpXVca3KhxnfYQ << excellent
https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=tpd5s116&fileType=pdf
CONCLUSION
Yes 300 Ω is adequate.