Mosaic
Well-Known Member
Hello:
Here is a code snip of the 16f690 assembly followed by the same as disassembled from the (MPLAB) hex file.
Assembly:
Disassembly:
The question is I don't understand why the 'MOVWF TRISC' instruction disassembles as a ' MOVWF 0x07'. Since you note that the CLR PORTC instruction is disassembled as a 'CLR 0x07'. It appears that the TRISC register is considered the SAME as the PORTC register, which can't be.
Now the TRISC register is 0x87 in the 16f690 which is 0x07 with bit 7 set. Is it that the MOVWF 0x07 instruction is actually using address 0x87 as a result of the previous bankselect setting? I suspect this maybe so as there are only 7 bits reserved for addressing in the 14 bit opcode, limiting the high address to 0x7F, thus requiring bank switching and the use of the RP0 / RP1 to make up 9 bits of addressing = 512 bytes.
If so then the CLR 0x07 (PORTC) needs a bankselect PORTC before it, otherwise it is overwriting the TRISC register? I observe that since TRISA and TRISC are in the same bank, bank switching between them does nothing.
Thanks.
Here is a code snip of the 16f690 assembly followed by the same as disassembled from the (MPLAB) hex file.
Assembly:
Code:
;Input PORTA setup (RA3)
Banksel TRISA
BSF TRISA,3 ; Set RA3 as an input
;PORTC setup
BankSel TRISC
movlw b'11110000'
movwf TRISC ; MAKE I/O PIN C0,c1,c2,c3 AN OUTPUT, BY SETTING PINS 0,1,2,3 LOW.
CLRF PORTC; init PORTC
BankSel Clicks ; back to general variable bank
Disassembly:
Code:
BSF STATUS,RP0
BCF STATUS,RP1
BSF PORTA,3
BSF STATUS,RP0
BCF STATUS,RP1
MOVLW 0xF0
MOVWF 0x07
CLRF 0x07
BCF STATUS,RP0
BCF STATUS,RP1
The question is I don't understand why the 'MOVWF TRISC' instruction disassembles as a ' MOVWF 0x07'. Since you note that the CLR PORTC instruction is disassembled as a 'CLR 0x07'. It appears that the TRISC register is considered the SAME as the PORTC register, which can't be.
Now the TRISC register is 0x87 in the 16f690 which is 0x07 with bit 7 set. Is it that the MOVWF 0x07 instruction is actually using address 0x87 as a result of the previous bankselect setting? I suspect this maybe so as there are only 7 bits reserved for addressing in the 14 bit opcode, limiting the high address to 0x7F, thus requiring bank switching and the use of the RP0 / RP1 to make up 9 bits of addressing = 512 bytes.
If so then the CLR 0x07 (PORTC) needs a bankselect PORTC before it, otherwise it is overwriting the TRISC register? I observe that since TRISA and TRISC are in the same bank, bank switching between them does nothing.
Thanks.
Last edited: