How in the world can you measure a voltage using only one probe?? The black probe MUST be connected to ground (0V) to measure voltage. The meter has 10M between its probes so it loads the measurement point with 10M to ground.Grouned by the 10meg ohm probe? I thought the DVM fluke 87 was floating from ground, so there is an internal ground inside the fluke meter? or how does it get grounded?
We do not know how close your unshielded meter probe and its wire are from electrical wiring in the walls, floor or ceiling.So the interference picked up has a high voltage?
Don't be silly. Interference in the air has no resistance.or resistance?
The output of a 148 opamp with a voltage of about +12.5V feeds a 100k (0.1M) series resistor to the input of a 4001 NOR gate. If you put the red probe of the meter on the NOR input and put the black probe on 0V then you have a 0.1M and 10M voltage divider.which loads and creates a voltage divider when I put the DVM probe on the node?
Absolutely NOT.Some Logic Probes have a Switch from TTL to CMOS switch , this switch must change the probes impedance from 120K TTL to 1K for CMOS right?
The hum and/or radio interference picked up by an unshielded probe and its wire can easily cause logic lows at 60 times per second.If the Logic Level is a HIGH state let's say +5 volts , putting .018 millivolts potential + 10M ohms probe loading it to ground + interference hum etc. = a voltage divider which load down the +5 volts to cause the input GATE to switch output states? isn't this right?
I got that WRONG!!!!The hum and/or radio interference picked up by an unshielded probe and its wire can easily cause logic lows at 60 times per second.
Put foil on your DVM leads for shield's, no weight don't do it!So what Meter probes can I get that are shielded?
In post #38 you wrongly said the logic probe had an input resistance of 1k when switched to Cmos. That is much too low.I don't know why a 20K impedance would be a short to a CMOS gates input?
You are not measuring the voltage or logic level of an input that is not driven by something. Instead you are measuring the output of the circuit that is driving the gate input.CMOS gate input is 1000Megs in parallel with 20K logic analyser probe impedance = a voltage drop of what?
TTL gate input is 1meg in parallel with 20K logic analyser probe impedance = a voltage drop of what?
I said many times, connect your 'scope probe to the red probe of your DVM to see all the hum and interference the red probe and its wire are picking up.Also I don't get how Hum and interference , has no resistance , but it creates loading and a voltage drop
Correct.I know hum and interference injects voltage or adds voltage
Sorry. I should have said that it might cause high, low, high, low over and over at 120Hz (a 60Hz square wave covered with radio and TV signals.)You said that hum and interference will cause a LOW logic level, can it cause a HIGH logic level? or just a LOW logic level?
Again, you are not measuring the voltage or logic level of an input that is not driven by something. Instead you are measuring the output of the circuit that is driving the gate input.The 10Meg ohms on an oscilloscope probe is 10meg ohms in parallel with a TTL gates input , which is a voltage drop and cause "load down" the voltage on the TTL or CMOS input gate
The Cmos ICs in this circuit use a 13V power supply so their output high voltage is +13V if their load current is very low.Billy Mayo, The Only thing you should be measuring on these devices with a voltmeter is the Output Pins.
And they should be Either HIGH or LOW.
Cmos, High is 5 Volts, Give or take a few Millivolts.
Cmos, Low is Zero Volts, Give or take a few Millivolts.
RTL, DTL then TTL logic ICs used 5V. Newer high speed Cmos (74HCxxxx0 ICs also use 5V. 4000 series Cmos can have a supply from 3V to 18V or 22V.Why do some circuits use +5 volts for high and other circuits use+10, +13 or +15 for the High State? what's the difference it having logic levels that are high voltage? any reason?
Please look it up on their datasheets.What is the maximum current a TTL input can have?
What is the maximum current a CMOS input can have?
You do not have a clue about simple electronics.My O-scope has a Probe Test Point Reference, it's at 500 Millivolts peak to peak, so 250 millivolts peak
Can I use this 250 millivolts peak voltage to inject a Logic IC input like a logic pulsar? would 250 millivolts be enough to pass the threshold voltage of TTL and CMOS IC chips?
RTL, DTL then TTL logic ICs used 5V. Newer high speed Cmos (74HCxxxx0 ICs also use 5V. 4000 series Cmos can have a supply from 3V to 18V or 22V.
What is the maximum current a TTL input can have?
What is the maximum current a CMOS input can have?Please look it up on their datasheets.
You also do not know that the negative part of the signal might destroy a logic input.
The logic high voltage of TTL is about 2.3V, not 5V. ITS SUPPLY voltage is 5V and I don't know why.Yes I know, But what is the Reason why a circuit or design want's to use a different Logic HIGH voltage level beside 5 volts? what is the advantage of using +18 or +22 for a high state, why?
Why do you say SAFE? A logic low is an input shorted to ground. The design limits the current.What is the maximum current SAFE zone for both of these ?
Because it is designed to use only positive voltages.Why can negative voltage can destroy the logic input?
Cmos can use a wide range of supply voltage and since its input current is nothing then its output when driving another Cmos is 0V to its positive supply voltage.
A TTL logic low input current is 1.6mA maximum. A 74LSxxx input current is 0.4mA max.
Cmos input current is nothing and its max output current depends on its supply voltage.
.Why can negative voltage can destroy the logic input?Because it is designed to use only positive voltages
TTL has only a 5V supply. Its high and low input voltages are specified.So there is really no reason why there is different logic levels for the high state?
The design of TTL limits its maximum input low current to 1.6mA. Cmos has no input current because its transistors are all Mosfets.When my manager is troubleshooting a Logic circuit, he takes a external power supply and puts the current limiter to MAX. I told him this can damage the TTL or CMOS chips but he said that the TTL or CMOS chip will just draw as much current as it needs so you can put the current limiter to max. My manager will inject a +5 volts direct on the input pin of a TTL or CMOS IC chips to test it's inputs and outputs works with the truth table.
For TTL IC chips you should set the current limiter to 1.6 mA?
For CMOS IC chips you should set the current limiter to > ?
An input voltage within the logic IC's total supply voltage range is normal and does no harm.I also thought it's bad for the Logic Chip to inject a constant voltage level which damages the Logic IC chip right?
Some ICs work only with pulses and not with DC inputs.That's why it's better to use a logic pulsar
There is never any reason to put a negative input voltage on a logic IC.You mean only for TTL IC? or for CMOS?
I don't do things WRONG so I don't know what is damaged.What does it damage?
Did you blow it up by injecting the input with MINUS 12V? Why?I think one of those circuit's i should you had a NOR GATE that went bad because it only would work when a +12 High state was inputted, When I would inject a - High State of ( - ) 12 volts the output was dead
The design of TTL limits its maximum input low current to 1.6mA. Cmos has no input current because its transistors are all Mosfets.
A TTL logic high input voltage is from 2.0V to 5.0V and its current is fairly low. A Cmos logic high input voltage is a percentage of its supply voltage up to the supply voltage.
Did you blow it up by injecting the input with MINUS 12V? Why?
Some ICs work only with pulses and not with DC inputs.
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