Current Circuits, DVM meter will short out when measuring on current circuits

Oh the switch on the probe changes the voltage threshold!
Man you make me look clever
https://www.radio-electronics.com/info/t_and_m/logic-probes/logic-probe-basics.php

have a read there

I point blank refuse to answer the interference question, on the grounds that you didnt think you just asked

Billy Mayo said:

Grouned by the 10meg ohm probe? I thought the DVM fluke 87 was floating from ground, so there is an internal ground inside the fluke meter? or how does it get grounded?

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How in the world can you measure a voltage using only one probe?? The black probe MUST be connected to ground (0V) to measure voltage. The meter has 10M between its probes so it loads the measurement point with 10M to ground.

So the interference picked up has a high voltage?

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We do not know how close your unshielded meter probe and its wire are from electrical wiring in the walls, floor or ceiling.

or resistance?

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Don't be silly. Interference in the air has no resistance.

which loads and creates a voltage divider when I put the DVM probe on the node?

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The output of a 148 opamp with a voltage of about +12.5V feeds a 100k (0.1M) series resistor to the input of a 4001 NOR gate. If you put the red probe of the meter on the NOR input and put the black probe on 0V then you have a 0.1M and 10M voltage divider.
Simple arithmetic shows that when you have the 12.5V across the 10.1M then you have 12.4V across the 10M meter and at the input of the NOR gate.

Some Logic Probes have a Switch from TTL to CMOS switch , this switch must change the probes impedance from 120K TTL to 1K for CMOS right?

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Absolutely NOT.
1k is almost a dead short to Cmos. Look at the logic probe again.

If the Logic Level is a HIGH state let's say +5 volts , putting .018 millivolts potential + 10M ohms probe loading it to ground + interference hum etc. = a voltage divider which load down the +5 volts to cause the input GATE to switch output states? isn't this right?

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The hum and/or radio interference picked up by an unshielded probe and its wire can easily cause logic lows at 60 times per second.

Can hum or interference cause a logic high? Or just a logic low?

so him and radio interference don't load down the logic level? They arent a voltage divider cause hum and air is not resistance

The hum and/or radio interference picked up by an unshielded probe and its wire can easily cause logic lows at 60 times per second.

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I got that WRONG!!!!
I am having a stupidity day! Or there is a contagious version going around

So what Meter probes can I get that are shielded?

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Put foil on your DVM leads for shield's, no weight don't do it!

Logic Analyzer probe impedance's are 20K , some are 1 meg

**broken link removed**

Logic Probe that has an input impedance of 7.5K

This would look like a short to a CMOS chip right?

http://www.barrytech.com/tektronix/probes/tekp6401.html

Foil makes a lousy shield for cables.

You do not want to use the multiple-wires logic analyser to see the input or output of a single gate.

I do not know why you posted the spec's for a Tektronic Logic Probe that is made for TTL ONLY. Its high and low voltages are not correct for 4xxx Cmos logic.
You said you use a logic probe with a TTL/Cmos switch. Please post its spec's.

No , I said that a Logic Probe has a switch , to switch from TTL to CMOS

That switch changes the threshold voltages for the Logic Probe also well I think the input impedance

TTL input impedance is different than an CMOS input impedance

I don't know why a 20K impedance would be a short to a CMOS gates input?
CMOS gate input is 1000Megs in parallel with 20K logic analyser probe impedance = a voltage drop of what?
TTL gate input is 1meg in parallel with 20K logic analyser probe impedance = a voltage drop of what?

Also I don't get how Hum and interference , has no resistance , but it creates loading and a voltage drop

I know hum and interference injects voltage or adds voltage

You said that hum and interference will cause a LOW logic level, can it cause a HIGH logic level? or just a LOW logic level?

The 10Meg ohms on an oscilloscope probe is 10meg ohms in parallel with a TTL gates input , which is a voltage drop and cause "load down" the voltage on the TTL or CMOS input gate

Billy Mayo said:

I don't know why a 20K impedance would be a short to a CMOS gates input?

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In post #38 you wrongly said the logic probe had an input resistance of 1k when switched to Cmos. That is much too low.
But earlier (post #36) you said it was 120k ohms or 1M ohms which is fine for Cmos.

CMOS gate input is 1000Megs in parallel with 20K logic analyser probe impedance = a voltage drop of what?
TTL gate input is 1meg in parallel with 20K logic analyser probe impedance = a voltage drop of what?

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You are not measuring the voltage or logic level of an input that is not driven by something. Instead you are measuring the output of the circuit that is driving the gate input.

Also I don't get how Hum and interference , has no resistance , but it creates loading and a voltage drop

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I said many times, connect your 'scope probe to the red probe of your DVM to see all the hum and interference the red probe and its wire are picking up.

I know hum and interference injects voltage or adds voltage

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Correct.

You said that hum and interference will cause a LOW logic level, can it cause a HIGH logic level? or just a LOW logic level?

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Sorry. I should have said that it might cause high, low, high, low over and over at 120Hz (a 60Hz square wave covered with radio and TV signals.)

The 10Meg ohms on an oscilloscope probe is 10meg ohms in parallel with a TTL gates input , which is a voltage drop and cause "load down" the voltage on the TTL or CMOS input gate

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Again, you are not measuring the voltage or logic level of an input that is not driven by something. Instead you are measuring the output of the circuit that is driving the gate input.
The 'scope probe is made with a very high resistance so that IT DOES NOT LOAD DOWN most circuits.

The datasheet for all 74xx TTL logic ICs shows that their maximum input low current is 1.6mA and a good input low voltage is 0.4V. Then a resistance of 0.4V/1.6mA= 250 ohms or less to ground will make a TTL input a logic low. Then why are you worried about 10 MILLION ohms?

Billy Mayo, The Only thing you should be measuring on these devices with a voltmeter is the Output Pins.
And they should be Either HIGH or LOW.
Cmos, High is 5 Volts, Give or take a few Millivolts.
Cmos, Low is Zero Volts, Give or take a few Millivolts.

Measuring Inputs is almost useless with any Voltmeter, because in many cases the signal is a SHARP SPIKE.
SometimesCapacitor Coupled.
But Either way, Too Fast for any Voltmeter.

But OK to be seen on a OSCILLOSCOPE.

chemelec said:

Billy Mayo, The Only thing you should be measuring on these devices with a voltmeter is the Output Pins.
And they should be Either HIGH or LOW.
Cmos, High is 5 Volts, Give or take a few Millivolts.
Cmos, Low is Zero Volts, Give or take a few Millivolts.

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The Cmos ICs in this circuit use a 13V power supply so their output high voltage is +13V if their load current is very low.

BRAIN DEAD........YES, Sorry I Ment to say for TTL is 5 Volts.

Cmos Outputs is usually at Supply Voltages.

Why do some circuits use +5 volts for high and other circuits use+10, +13 or +15 for the High State? what's the difference it having logic levels that are high voltage? any reason?

What is the maximum current a TTL input can have?
What is the maximum current a CMOS input can have?

My O-scope has a Probe Test Point Reference, it's at 500 Millivolts peak to peak, so 250 millivolts peak

Can I use this 250 millivolts peak voltage to inject a Logic IC input like a logic pulsar? would 250 millivolts be enough to pass the threshold voltage of TTL and CMOS IC chips?

Billy Mayo said:

Why do some circuits use +5 volts for high and other circuits use+10, +13 or +15 for the High State? what's the difference it having logic levels that are high voltage? any reason?

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RTL, DTL then TTL logic ICs used 5V. Newer high speed Cmos (74HCxxxx0 ICs also use 5V. 4000 series Cmos can have a supply from 3V to 18V or 22V.

What is the maximum current a TTL input can have?
What is the maximum current a CMOS input can have?

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Please look it up on their datasheets.

My O-scope has a Probe Test Point Reference, it's at 500 Millivolts peak to peak, so 250 millivolts peak
Can I use this 250 millivolts peak voltage to inject a Logic IC input like a logic pulsar? would 250 millivolts be enough to pass the threshold voltage of TTL and CMOS IC chips?

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You do not have a clue about simple electronics.
You do not know that the 'scope test signal is AC and you also do not know that the AC probably swings above (+) and below (-) ground.
You also do not know that the negative part of the signal might destroy a logic input.

The threshold voltages for TTL and Cmos are listed on their datasheets and I think you posted them here. 250mV peak is much too small.

RTL, DTL then TTL logic ICs used 5V. Newer high speed Cmos (74HCxxxx0 ICs also use 5V. 4000 series Cmos can have a supply from 3V to 18V or 22V.

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Yes I know, But what is the Reason why a circuit or design want's to use a different Logic HIGH voltage level beside 5 volts? what is the advantage of using +18 or +22 for a high state, why?

What is the maximum current a TTL input can have?
What is the maximum current a CMOS input can have?Please look it up on their datasheets.

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What is the maximum current SAFE zone for both of these ?

You also do not know that the negative part of the signal might destroy a logic input.

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Why can negative voltage can destroy the logic input?

Billy Mayo said:

Yes I know, But what is the Reason why a circuit or design want's to use a different Logic HIGH voltage level beside 5 volts? what is the advantage of using +18 or +22 for a high state, why?

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The logic high voltage of TTL is about 2.3V, not 5V. ITS SUPPLY voltage is 5V and I don't know why.
Cmos can use a wide range of supply voltage and since its input current is nothing then its output when driving another Cmos is 0V to its positive supply voltage.

What is the maximum current SAFE zone for both of these ?

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Why do you say SAFE? A logic low is an input shorted to ground. The design limits the current.

A TTL logic low input current is 1.6mA maximum. A 74LSxxx input current is 0.4mA max.
A TTL logic low output current is 16mA max so it can drive up to 10 TTL inputs.
A 74LSxxxx logic low output current is 8mA max.
Cmos input current is nothing and its max output current depends on its supply voltage.
Why am I saying all this when it is on the datasheets?

Why can negative voltage can destroy the logic input?

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Because it is designed to use only positive voltages.

Cmos can use a wide range of supply voltage and since its input current is nothing then its output when driving another Cmos is 0V to its positive supply voltage.

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So there is really no reason why there is different logic levels for the high state?

A TTL logic low input current is 1.6mA maximum. A 74LSxxx input current is 0.4mA max.
Cmos input current is nothing and its max output current depends on its supply voltage.

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When my manager is troubleshooting a Logic circuit, he takes a external power supply and puts the current limiter to MAX. I told him this can damage the TTL or CMOS chips but he said that the TTL or CMOS chip will just draw as much current as it needs so you can put the current limiter to max. My manager will inject a +5 volts direct on the input pin of a TTL or CMOS IC chips to test it's inputs and outputs works with the truth table.

For TTL IC chips you should set the current limiter to 1.6 mA?
For CMOS IC chips you should set the current limiter to > ?

I also thought it's bad for the Logic Chip to inject a constant voltage level which damages the Logic IC chip right?

That's why it's better to use a logic pulsar

Why can negative voltage can destroy the logic input?Because it is designed to use only positive voltages

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.

You mean only for TTL IC? or for CMOS?

What does it damage?

I think one of those circuit's i should you had a NOR GATE that went bad because it only would work when a +12 High state was inputted, When I would inject a - High State of ( - ) 12 volts the output was dead

Billy Mayo said:

So there is really no reason why there is different logic levels for the high state?

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TTL has only a 5V supply. Its high and low input voltages are specified.
Cmos has a wide range of supply voltage so its high and low input voltages are a percentage of its supply voltage.

When my manager is troubleshooting a Logic circuit, he takes a external power supply and puts the current limiter to MAX. I told him this can damage the TTL or CMOS chips but he said that the TTL or CMOS chip will just draw as much current as it needs so you can put the current limiter to max. My manager will inject a +5 volts direct on the input pin of a TTL or CMOS IC chips to test it's inputs and outputs works with the truth table.

For TTL IC chips you should set the current limiter to 1.6 mA?
For CMOS IC chips you should set the current limiter to > ?

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The design of TTL limits its maximum input low current to 1.6mA. Cmos has no input current because its transistors are all Mosfets.
A TTL logic high input voltage is from 2.0V to 5.0V and its current is fairly low. A Cmos logic high input voltage is a percentage of its supply voltage up to the supply voltage.

I also thought it's bad for the Logic Chip to inject a constant voltage level which damages the Logic IC chip right?

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An input voltage within the logic IC's total supply voltage range is normal and does no harm.

That's why it's better to use a logic pulsar

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Some ICs work only with pulses and not with DC inputs.

You mean only for TTL IC? or for CMOS?

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There is never any reason to put a negative input voltage on a logic IC.

What does it damage?

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I don't do things WRONG so I don't know what is damaged.

I think one of those circuit's i should you had a NOR GATE that went bad because it only would work when a +12 High state was inputted, When I would inject a - High State of ( - ) 12 volts the output was dead

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Did you blow it up by injecting the input with MINUS 12V? Why?

The design of TTL limits its maximum input low current to 1.6mA. Cmos has no input current because its transistors are all Mosfets.
A TTL logic high input voltage is from 2.0V to 5.0V and its current is fairly low. A Cmos logic high input voltage is a percentage of its supply voltage up to the supply voltage.

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So I can use an external power supply and inject a logic HIGH with the current limit set to MAX all the way ? I thought it was bad to do this

So I can set the current limit to MAX on the external power supply and it will cause no harm or damage to the logic input TTL or CMOS?

My Manager will take a jumper from ground to make a logic low when there is a logic high of +18 or +22 , he will take a jump and jump the input high +22 straight direct to ground. Is this good or bad? no bleeder resistor needed or a capacitor needed with the jumper to ground to make a logic low?

Did you blow it up by injecting the input with MINUS 12V? Why?

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No, It was the design of the circuit, the NOR GATE can input a +12 volts or a - 12 volts on the input

Some ICs work only with pulses and not with DC inputs.

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Which Logic IC only work with pulse and not with DC inputs?

These you have to use a logic pulsar to verify the inputs and outputs right?