Current Circuits, DVM meter will short out when measuring on current circuits

[Billy Mayo]

Servo Ground To Chassis Ground was 17.6 Millivolts SORRY guys

 

[Billy Mayo]

Do you have to use an oscilloscope when testing logic Gate that have no pull down resistor or pull up resistors? because the DVM meter will trip the gates input?

My Manager said when a gate doesn't have a pull down resistor , the gates input is high impedance or floating voltage, so when you put your DVM meter probe is either discharges and trips the gates input threshold or it ADD the gates input high impedance + the parallel DVM meter's impedance which causes the gates input to trips its output

 

[audioguru]

.
is this a common problem?

You are the first person I heard about who uses a DVM to measure logic levels on Cmos Logic ICs. When I troubleshooted Cmos logic I didn't even think about using a DVM that picks up mains hum, local radio stations and many communications.

I guess the DVM probes are low impedance and not shielded

I posted the input impedance of the Fluke 87 DVM as TEN MILLION ohms which is not a low impedance, it is a very high impedance.
The probe and its wire are unshielded so they act like an antenna, especially when they feed the very high impedance of the DVM.

What should it be called?

You are measuring logic levels with the wrong instrument. It should be called, "How to waste time by using as DVM to measure logic levels".

What is this called? what kind of test or check am I doing

You were measuring the voltage drop across ground busses.

 

[Billy Mayo]

You are the first person I heard about who uses a DVM to measure logic levels on Cmos Logic ICs. When I troubleshooted Cmos logic I didn't even think about using a DVM that picks up mains hum, local radio stations and many communications.

Is this the same for measuring logic levels for TTL?

Sorry I never knew this, all the techs at all my jobs i had always used a DVM meter to measure logic levels for TTL and CMOS

The probe and its wire are unshielded so they act like an antenna, especially when they feed the very high impedance of the DVM.

Doesn't the very high impedance BLOCK the unshielded noises, hum , etc.

You're saying the DVM meter will amplifier this right?

You were measuring the voltage drop across ground busses.

Thanks for the name

This voltage drop is in the millivolts

Is this a potential difference? and can this make a difference when probing around on logic levels by not having the correct reference to ground ?

 

[4pyros]

Doesn't the very high impedance BLOCK the unshielded noises, hum , etc.

You're saying the DVM meter will amplifier this right?

No and No

 

[Billy Mayo]

So you guys never use a DVM meter to measure logic level for TTL or CMOS?

Or do you have to get DVM meter probes that are shielded?

 

[4pyros]

So you guys never use a DVM meter to measure logic level for TTL or CMOS?

Or do you have to get DVM meter probes that are shielded?

I use a logic probe like this;

 

[Billy Mayo]

Why should I use a Logic Probe? is the probe high impedance or doesn't pick up hum or noises?

What is the theory behind it please?

 

[Reloadron]

Billy, I can't help but believe this thread may go much better if you could post some schematics and define exactly what you are working on. Much like the other thread once some drawings were posted things became very clear.

Ron

 

[Billy Mayo]

I don't understand the difference between a logic probe VS a Fluke DVM 87

What is the differences when measuring logic levels?

 

[audioguru]

Is this the same for measuring logic levels for TTL?

If you ever learn about electronics then you might learn about the differences between TTL and Cmos logic ICs.
I never used a DVM for measuring logic levels for TTL nor for Cmos.

Doesn't the very high impedance BLOCK the unshielded noises, hum , etc.

No. The opposite.
A high impedance picks up interference from the air. A low impedance shorts interference to ground.
A shield blocks interference.

You're saying the DVM meter will amplifier this right?

No, a DVM set to show volts is not an amplifier. It simply shows how many volts of interference its unshielded probe and wire pickup. It injects the interference into the circuit it is "testing".

Is this a potential difference? and can this make a difference when probing around on logic levels by not having the correct reference to ground ?

Instead of asking millions of questions about very simple electronics basics, you should learn things like the logic voltage levels of TTL and Cmos:
1) What is the maximum voltage for a TTL logic low (with a 5V supply)? What is the maximum TTL input current for a logic low?
2) What is the maximum voltage for a Cmos logic low (with a 5V supply)? What is the maximum Cmos input current?

 

[chemelec]

I think you should use the 'scope for measuring logic levels, not the DVM
Click to expand....

is this a common problem?

I AGREE, A Scope would be Much more Suitable.

I guess the DVM probes are low impedance and not shielded

10 Meg Ohm per Volt is NOT "Low Impedance"

This thread about a DVM (set for measuring volts) shorting out a circuit DOES NOT MAKE ANY SENSE. Click to expand...

What should it be called?

Possibly somewhat "Loading it down". Definately NOT Shorting it.

When your Input Impedance on C-Mos devices is 100,000,000,000 Ohms, Than Yes the 10M Ohm per Volt will somewhat pull it down.
Also the LEAD CAPACITANCE will create a tiny, Momentary current draw, When making Connection.

Signal Ground to DC ground was 10 millivolts
Signal Ground to Servo ground was 16.2 millivolts
Signal Ground to Chassis Ground was 1.4 Millivolts

DC ground to Servo Ground was 6 Millivolts
DC ground to Chassis Ground was 11.2 millivolts

Servo Ground To Chassis Ground was 17.6 volts
Click to expand...
What is this called? what kind of test or check am I doing​

A Bunch of Mindless Tests.
What is the POINT TO MAKING THESE TESTS?
Is there any Schematic Info telling you What readings you should get?
​

 

[Billy Mayo]

Possibly somewhat "Loading it down". Definately NOT Shorting it.

How is a 10 Meg ohm DVM meter loading it down? or pulling it down?

Are you saying it's a voltage divider?

Also the LEAD CAPACITANCE will create a tiny, Momentary current draw, When making Connection.

So the Probe lead has capacitance making connection with the PCB board trace or node capacitance , creates a current draw?

 

[Billy Mayo]

a DVM set to show volts is not an amplifier. It simply shows how many volts of interference its unshielded probe and wire pickup. It injects the interference into the circuit it is "testing".

So what Meter probes can I get that are shielded?

No. The opposite.
A high impedance picks up interference from the air. A low impedance shorts interference to ground.
A shield blocks interference.

An Oscilloscope probe is 10 megs, I just measured it today and now you're saying that High Impedance is picking up interference , etc.
So how is an O-scope good to measure logic levels when it's high impedance?

An Analog Meter is low impedance, is this better to use when measuring logic state or what is a problem with using an analog meter when testing logic levels?

I don't understand the difference between a logic probe VS a Fluke DVM 87
What is the differences when measuring logic levels?

So a Logic Probe, so low impedance ? and has shielding?

 

[Billy Mayo]

Signal Ground to DC ground was 10 millivolts
Signal Ground to Servo ground was 16.2 millivolts
Signal Ground to Chassis Ground was 1.4 Millivolts

DC ground to Servo Ground was 6 Millivolts
DC ground to Chassis Ground was 11.2 millivolts

Servo Ground To Chassis Ground was 17.6 millivolts

What is this called? what kind of test or check am I doingA Bunch of Mindless Tests.
What is the POINT TO MAKING THESE TESTS?
Is there any Schematic Info telling you What readings you should get?

Why is there potential differences? and where does the potential differences come from?

When I measured ohms between each ground , it was in the milliohms , so they are tied together and not isolated? what would I measure in ohms to know if the grounds are isolated?

 

[Billy Mayo]

Instead of asking millions of questions about very simple electronics basics, you should learn things like the logic voltage levels of TTL and Cmos:
1) What is the maximum voltage for a TTL logic low (with a 5V supply)? What is the maximum TTL input current for a logic low?
2) What is the maximum voltage for a Cmos logic low (with a 5V supply)? What is the maximum Cmos input current?

Logic Probe Input Impedance is either 1 meg ohms or 120K

TTL: Logic “1” (Hi LED)··············································>2.3±0.2V DC >3.0±0.25V
Logic “0” (Lo LED)·············································<0.8±0.2V DC <0.75±0.25V
CMOS: Logic “1” (Hi LED)··············································>70% Vcc±10% >60% Vcc±5%
Logic “0” (Lo LED)·············································<30% Vcc±10% <15% Vcc±5%

Logic 1
TTL: > 2.3V ±0.02V
CMOS: > 70% Vcc ± 10%
Logic 0
TTL: < 0.08V ±0.02V
CMOS: < 30% Vcc ± 10%

 

[audioguru]

How is a 10 Meg ohm DVM meter loading it down? or pulling it down?
Are you saying it's a voltage divider?

The only schematic you showed us has two 148 opamps feeding the inputs of a 4001 NOR gate through 100k series resistors. All of them are powered from +13V.
When the outputs of the opamps are high then they are about +12.5V. If you connect a 10M ohm probe to an input of the NOR gate then the voltage divider caused by the 100k resistor being loaded to ground by the 10M ohm probe causes the +12.5V to drop to +12.4V.
But the Cmos logic low is about +3.9V or less so THERE IS NO WAY that the resistance of the probe causes the logic high to be low enough for the Gate to change states but interference picked up can.

So the Probe lead has capacitance making connection with the PCB board trace or node capacitance , creates a current draw?

The probe has such a small amount of capacitance then I don't think it will cause logic to change states but interference picked up can.

So what Meter probes can I get that are shielded?

An oscilloscope probe and a logic probe are both shielded and are suitable for testing logic inputs. A DVM is not.
Oh, maybe you can use a DVM if you are in the middle of the Sahara desert (or on the planet Venus) where there is no mains hum and no radio interference.

An Oscilloscope probe is 10 megs, I just measured it today and now you're saying that High Impedance is picking up interference , etc.
So how is an O-scope good to measure logic levels when it's high impedance?
An Analog Meter is low impedance, is this better to use when measuring logic state or what is a problem with using an analog meter when testing logic levels?

Why don't you understand that the ordinary wire and probe connected to the input of the DVM are an antenna? They pickup mains hum and interference from the air because they are not shielded and because they feed the high input impedance of the meter then the interference does not have a low impedance voltage divider to ground. Connect your 'scope probe to the red wire of your DVM to SEE the hum and interference.
A 'scope probe and its wire and a logic probe are shielded so they do not pickup interference then their high impedance is good, it is not bad.

So a Logic Probe, so low impedance ? and has shielding?

The impedance of a logic probe must be fairly high for it to measure your Cmos circuits. It is shielded so it does not pickup mains hum and interference.

Why is there potential differences? and where does the potential differences come from?
When I measured ohms between each ground , it was in the milliohms , so they are tied together and not isolated? what would I measure in ohms to know if the grounds are isolated?

The voltages are only a maximum of 0.018V above ground so of course they are tied together.
Does it matter? Will only o.018V at the input of TTL or Cmos logic cause it to be a logic high? No, because you discovered that the input of a gate must be at least a few volts to be a logic high then millivolts do not affect the logic.

 

[Billy Mayo]

100k resistor being loaded to ground by the 10M ohm probe causes the +12.5V to drop to +12.4V.

Grouned by the 10meg ohm probe? I thought the DVM fluke 87 was floating from ground, so there is an internal ground inside the fluke meter? or how does it get grounded?

But the Cmos logic low is about +3.9V or less so THERE IS NO WAY that the resistance of the probe causes the logic high to be low enough for the Gate to change states but interference picked up can.

So the interference picked up has a high voltage? or resistance? which loads and creates a voltage divider when I put the DVM probe on the node?

The impedance of a logic probe must be fairly high for it to measure your Cmos circuits

.

Some Logic Probes have a Switch from TTL to CMOS switch , this switch must change the probes impedance from 120K TTL to 1K for CMOS right?

Will only o.018V at the input of TTL or Cmos logic cause it to be a logic high? No, because you discovered that the input of a gate must be at least a few volts to be a logic high then millivolts do not affect the logic.

If the Logic Level is a HIGH state let's say +5 volts , putting .018 millivolts potential + 10M ohms probe loading it to ground + interference hum etc. = a voltage divider which load down the +5 volts to cause the input GATE to switch output states? isn't this right?

 

[large_ghostman]

Grouned by the 10meg ohm probe? I thought the DVM fluke 87 was floating from ground, so there is an internal ground inside the fluke meter? or how does it get grounded?

You cant be asking this??? think about it, you have two probes on the meter, one is probably red, one might be black, the black one you stick on the part of the circuit that goes to GROUND, the red one you stick anywhere else, it makes a circuit. So unless it's a open circuit, current goes from the black one (ok lets say red one because i am not going there) into the meter, then out the other probe to complete the circuit

 

[large_ghostman]

Grouned by the 10meg ohm probe? I thought the DVM fluke 87 was floating from ground, so there is an internal ground inside the fluke meter? or how does it get grounded?



So the interference picked up has a high voltage? or resistance? which loads and creates a voltage divider when I put the DVM probe on the node?

.

Some Logic Probes have a Switch from TTL to CMOS switch , this switch must change the probes impedance from 120K TTL to 1K for CMOS right?



If the Logic Level is a HIGH state let's say +5 volts , putting .018 millivolts potential + 10M ohms probe loading it to ground + interference hum etc. = a voltage divider which load down the +5 volts to cause the input GATE to switch output states? isn't this right?

Ohms law
5V with a 10M load =

5/10,000000=0.0000005 amps! so 18 milli volts with 0.0000005A against 5V
Which do you think will win?