common collector NPN questions

[philba]

I have been looking at the common collector configuration of an NPN transistor and can't fiugre out why it works the way it does. I've not found anything online that helps me understand this. Horowitz/Hill only has a brief section on it.

By the way, the CC config looks like a nice way to reduce input voltage with out dividing it and thus increasing impedence. Of couse, you have to deal with Vbesat drop.

So, my main question is why is the output voltage at the emitter limited to the base voltage (minus Vbesat). What is the mechanism? Maybe a better way to ask it is why is the voltage gain approximately 1 (actually (Vb - Vbesat)/Vb )?

 

[Papabravo]

The simple answer is that Vbe must be greater than about 0.7 volts for the transistor to be on. The collector is clamped to the supply voltage. As the transistor turns on and current begins to flow that current raises the potential of the emitter which reduces Vbe and trys to turn it off. To keep the transistor on Vb has to rise.

No matter what you do with the supply on the base, the output will never be greater than the 5V on the collector. With the base supply at 15V, the base resistor will drop 9.5 volts, Vb will be about 5.5V, and the output will be about 4.8V assuming Vce to be about 0.2V. Note that Vbe is pegged at about 0.7V

 

[Roff]

I have been looking at the common collector configuration of an NPN transistor and can't fiugre out why it works the way it does. I've not found anything online that helps me understand this. Horowitz/Hill only has a brief section on it.

By the way, the CC config looks like a nice way to reduce input voltage with out dividing it and thus increasing impedence. Of couse, you have to deal with Vbesat drop.

So, my main question is why is the output voltage at the emitter limited to the base voltage (minus Vbesat). What is the mechanism? Maybe a better way to ask it is why is the voltage gain approximately 1 (actually (Vb - Vbesat)/Vb )?

Actually, the voltage gain is not (Vb - Vbesat)/Vb. The small-signal gain is approximately Rload/(re+Rload), where Rload is the equivalent resistance to AC ground from the emitter, and re is the dynamic emitter resistance, which is approximately equal to 0.026/Ie, where Ie is the DC emitter current in Amps.
This approximation omits the resistance of the source, and the intrinsic base resistance (which, if it were included, would be divided by (beta+1) and then added into the denominator term), as well as some other generally insignificant terms.

 

[hawk2eye]

I have been looking at the common collector configuration of an NPN transistor and can't fiugre out why it works the way it does. I've not found anything online that helps me understand this. Horowitz/Hill only has a brief section on it.

By the way, the CC config looks like a nice way to reduce input voltage with out dividing it and thus increasing impedence. Of couse, you have to deal with Vbesat drop.

So, my main question is why is the output voltage at the emitter limited to the base voltage (minus Vbesat). What is the mechanism? Maybe a better way to ask it is why is the voltage gain approximately 1 (actually (Vb - Vbesat)/Vb )?

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look in Horowitz/ Hill p70, fig 2.16 that explains the
AC coupled emitter follower,(or CC) the design is also shown.

Your drawing is true for a simulation, but neglects the bias circuit.
A capacitor is often used to couple the signal into a circuit to avoid disturbing DC input bias voltage.

A second capacitor is often used to couple the circuit output to a load : to avoid DC loading .

hawk2eye