Combinatoric timing problem

[Grossel]

I have a combinatoric circuit that will reset a stage (one of several sr-flipflops).
**broken link removed**

Then I discovered that if both A (set-button) and B (from reset button) goes high at same time (like if they're wired together) that will cause S to go high for some ns and then go because of delay in leftmost and gate.

Then I start working boolean algebra, but I won't get any similar circuit that won't producing spikes when A and B shift state same time.

Also I would like trying avoiding any aditional delay circuits that hasn't other purposes than only delay the signal.

Any ideas?

 

[Mikebits]

This is the nature of combinatorial logic. Sequential logic is the fix, but this adds delay...

 

[Jules_Theone]

Add a buffer of the same type as the other gates on the 'A' input to the second gate. This will add a delay so both signals reach the second gate at the same time, minimising the delay between them.

 

[Grossel]

Add a buffer of the same type as the other gates on the 'A' input to the second gate. This will add a delay so both signals reach the second gate at the same time, minimising the delay between them.

I know I can do this easily, but as I mentioned in the first post, I want to avoid additional delay circuits.

I think it's impossible to achieve, can anybody confirm this?

What about an example on Sequential logic?

 

[Jules_Theone]

Its a compromise between speed and hazard elimination. The sequential circuit would produce a longer delay but eliminate the hazards.

Are you using the fastest logic family because if you use fast logic the delay will be minimised. The fastest i believe is 74G**.

 

[Grossel]

Its a compromise between speed and hazard elimination. The sequential circuit would produce a longer delay but eliminate the hazards.

Are you using the fastest logic family because if you use fast logic the delay will be minimised. The fastest i believe is 74G**.

At this moment, this is only a theoretical question, so the physical component isn't chosed yet. But I presuppose that all logic gates in the circuit provide roughly the same delay time.

But sure I get a very fast nand gate (the left one) and put in a slower one for the right. But then again, I probably have to spend more physical IC's on a board than neccesary just to provide a longer delay.
I think instead I can use two inverters in serie of same type (ttl-family) as the two and gates.

 

[Mikebits]

But why would set and reset be asserted at the same time? Is this a likely situation? Can you assign priority logic to A and B So A overides B? If so, Some sort of encoder logic can be used.

Also, why is delay a problem? A few usec should hardly be an issue compared to pressing a button. Using sequential logic like flipflops for your switches can ensure that a race condition does not exist.
Clock A on rising edge and B on falling edge. This does add complexity so you have to decide how important it is.

 

[Chaerl]

Try to see the propagation delay of each gates (semicondutors produces interal delays).

 

[Mikebits]

Try to see the propagation delay of each gates (semicondutors produces interal delays).

Prop delay for most gates these days is in the nano second range.

 

[Chaerl]

True, but sometimes its an issue if you're working at highspeed specially if the timing is critical

 

[Mikebits]

Since the poster mentioned buttons (as in a switch), I doubt nano or microseconds is an issure.

 

[Chaerl]

and the poster mentioned, causes S to go high for some ns and then go because of delay in leftmost and gate.

Initially, the inputs are lo. the complementary input of the right most gate is actually hi. at the switch turned to hi, because of the propagation delay of some ns of the left most gate, the complementary input is still hi for some ns while A changes to hi. so the output S stays hi for some ns. when the input of the left most gate propagates to the output, the complementary input becomes lo and thus, S becomes lo until the change of status.

 

[xpi0t0s]

It's impossible to solve directly because the truth table of your circuit is:

A B S
0 0 0
0 1 0
1 0 1
1 1 0

so when you get A=1 B=0 on the inputs, you WILL get a 1 on the output, and the question translates to "how can I delay A without delaying A" which is obviously a contradiction.

However there may be a solution. The circuit is equivalent to S=A.!B (i.e. run B through an inverter and AND it with A), so can you get !B from anywhere? If C=!B then the truth table becomes:

A C S
0 0 0
0 1 0
1 0 0
1 1 1

and there is no transient for AC=00->10->11, or in fact for 00->01->11, because both must go high before the output can.

 

[Grossel]

Old thread, but.

I found a web page with a lot of pdf's (legal I think) from another forum/thred wich I cannot remember. **broken link removed**.

Direct link to pdf file:
Advanced Logic Design Techniques in Asynchronous Sequential.

Name of technique is Hazard Suppression and is described in first part, right after T flip flop. However, I don't know if I can use this to solve problem above.

I think that xpi0t0s solution might be the only usable one. I guess using just a AND gate will provide any needed delay.