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Clock speed

Discussion in 'General Electronics Chat' started by Parth86, Jan 2, 2015.

  1. Parth86

    Parth86 Member

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    hello,
    I have some query
    Processor need fixed number of clock or cycle to execute instruction. I think different instruction take different cycle to execute. some instruction take one cycle, some instruction take two cycle

    Q1 the speed of processor depend on which parameter (data bit or address bit) ?
    Q2 can we choose any crystal for any mircocontroller (PIC, 8051,) ?
     
  2. MikeMl

    MikeMl Well-Known Member Most Helpful Member

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    The instructions that take more time are usually the ones where you have to do additional memory cycles or bank switching to fetch operands. For the short instructions, all of the data is already available either in the instruction word, or in the ALU.

    Not any crystal. There is always a spec for the highest allowed frequency, and sometimes for the lowest allowed frequency. The type of crystal, fundamental, overtone, series-resonant, parallel-resonant, load capacitance, or no crystal (replace with RC network) is specified on the microprocessor's Data Sheet.

    When in doubt, download, and study the data sheet.
     
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  3. Parth86

    Parth86 Member

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    I am reading this paragraph. I am trying to understand some basic. There is not enough explanation so I am asking here
    1Fetch the instruction from memory
    my explanation: read the program memory and store the instruction in instruction register.we need to component only
    program memory and instruction register

    2.Decode the instruction, and generate the necessary control signals
    my explanation: 8 bit instruction
    ADD A,R1
    4 bit for opcode like ADD, SUB, INC, ...
    4 bit for control signal like A, R1

    I don't understand last three instruction?
     
  4. dave

    Dave New Member

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  5. KeepItSimpleStupid

    KeepItSimpleStupid Well-Known Member Most Helpful Member

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    Remember there is RISC and CISC architectures. The sequence is generally Fetch, Decode and Execute with the PC pointing to the next instruction when complete.
    CISC architectures may require more than one cycle. e.g. ADD #A, (R1+)
     
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  6. Parth86

    Parth86 Member

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    CISC chips have an increasing number of components and an ever increasing instruction set and so are always slower and less powerful at executing “common” instructions. CISC chips execute an instruction in two to ten machine cycles

    RISC chips have fewer components and a smaller instruction set, allowing faster accessing of “common” instructions
    RISC chips execute an instruction in one machine cycle
    look this picture. this can executed three instruction
    MOV A,#immediate data
    MOV A, R1
    MOV R1,A

    upload_2015-1-4_3-48-11.png
    MOV A,#immediate data
    MOV A, R1
    MOV R1,A
    how many cycle I need to execute these instruction?. I think ,two because I don't need to decode signal. to execute the instruction we can fetch and directly execute instruction
     
  7. KeepItSimpleStupid

    KeepItSimpleStupid Well-Known Member Most Helpful Member

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    I cycle to be a fetch/decode/execute CYCLE. Not saying hat rising edge, could be fetch, the flat top decode and the trailing edge execute or three separate clock cycles.

    Each take time:
    Fetch: RAM/CORE/SWAP/CACHE take different times
    Decode: is largely logic probigation
    Execute: Probably in RISC it's shorter.
     
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  8. Parth86

    Parth86 Member

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    please check capability of circuit.
    can we execute following instruction with this circuit
    load ,store ,arithmetic and logic instruction
    upload_2015-1-4_12-4-20.png

    Note : I did not use 2 input 4 bit logic Ics. I don't have this Ic in software
    How to improve circuit ?
     
    Last edited by a moderator: Jan 3, 2015
  9. Parth86

    Parth86 Member

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    please help me , whats wrong with that circuit. just tell me few mistakes. I will modify the circuit. please help me
     

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