1) I've used 2K resistors for I2C stuff - it's not really critical.
2) Shorting the data lines to ground is probably a bad idea - at the very least, permanently tie the UB# line high which *should* keep the upper bus tristate - maybe...
3) You should check the bulk capacitance requirements - each part usually has some recommendations as to how much capacitance they want. Altera probably has an app note on power supply circuit recommendations, plus it never hurts to put a couple 'C' or 'D' sized Tant. pads scattered around the board. Keep the ceramics though - they serve different purposes. The ceramics are located within a couple mm of the chip and supply the power for the switching spikes, while the larger Tant's filter power supply ripple and lower frequency stuff.
**broken link removed**
4) Dunno, don't use PICs much
5) Depends on who you ask... Electrically the voltage between them should be very close to 0, it's a question of noise at that point. I don't think it matters too much - but it doesn't hurt to make sure it's not sitting next to the switching regulator, and it's data lines to the FPGA are short and low capacitance.
6) On Xilinx parts anyway, clk lines are usually for clock inputs - any IO lines can serve as clock "drivers". After spending 10 min poking through the Altera docs, it looks like it's the same, but I'm not exactly sure.
7) If you have a 4 layer board, use the two inner layers for power and ground. If you have more internal layers, it's preferred to keep things paired up so that when currents flow, they have a good return path, as well as keeping the board symmetrical. Since this is based on a FPGA, you should be able to juggle the pinouts in order to make routing as simple as possible - most of the busses should be top-side without having to do any weird bends/flips.
Also pay attention to the example layouts for the switching regulators - follow them as closely as possible, and do copperfills/isolated ground "islands" as they call for.
BTW, the DS2764 Sense line isn't wired up correctly - you should create another net called "BAT-" and wire that through the DS2764 instead of attaching the battery to Gnd.
2) Shorting the data lines to ground is probably a bad idea - at the very least, permanently tie the UB# line high which *should* keep the upper bus tristate - maybe...
3) You should check the bulk capacitance requirements - each part usually has some recommendations as to how much capacitance they want. Altera probably has an app note on power supply circuit recommendations, plus it never hurts to put a couple 'C' or 'D' sized Tant. pads scattered around the board. Keep the ceramics though - they serve different purposes. The ceramics are located within a couple mm of the chip and supply the power for the switching spikes, while the larger Tant's filter power supply ripple and lower frequency stuff.
**broken link removed**
4) Dunno, don't use PICs much
5) Depends on who you ask... Electrically the voltage between them should be very close to 0, it's a question of noise at that point. I don't think it matters too much - but it doesn't hurt to make sure it's not sitting next to the switching regulator, and it's data lines to the FPGA are short and low capacitance.
6) On Xilinx parts anyway, clk lines are usually for clock inputs - any IO lines can serve as clock "drivers". After spending 10 min poking through the Altera docs, it looks like it's the same, but I'm not exactly sure.
7) If you have a 4 layer board, use the two inner layers for power and ground. If you have more internal layers, it's preferred to keep things paired up so that when currents flow, they have a good return path, as well as keeping the board symmetrical. Since this is based on a FPGA, you should be able to juggle the pinouts in order to make routing as simple as possible - most of the busses should be top-side without having to do any weird bends/flips.
Also pay attention to the example layouts for the switching regulators - follow them as closely as possible, and do copperfills/isolated ground "islands" as they call for.
BTW, the DS2764 Sense line isn't wired up correctly - you should create another net called "BAT-" and wire that through the DS2764 instead of attaching the battery to Gnd.
. I have attached an updated version without the intenal sense resistor shorted. I'm glad you pointed that out. I'll prowl over the PSRAM datasheet a bit more to figure out what to do with the unused data lines. My guess is that I will leave the pins disconnected and tie the upper byte enable to high. Thanks again for your assistance!
