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Building a switcheable ramp generator circuit using multiplying DAC

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Hello,

I currently have a circuit that is built around two 74HC4040 and AD7533 setup in bipolar output. Currently I am using only 9bits of AD7533 at 30Hz reset rate. I have an analog switch added into the circuit to switch it to 60Hz, but as soon as I do that (eventually using only 8bits of AD7533), its not bipolar anymore. Is there anyway to implement this?

Desired output at double the frequency should be still a bipolar output with half the amplitude and two cycles per 30Hz cycle. Currenlty at double frequency it shifts to positive output rather than being bipolar. One can add offset to output and acheive this, but I want it to be automatic.

thanks
 

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AnalogKid

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U4 - the connection between Q9 and the reset input does not do anything. When Q9 goes high, forces a reset, and then is yanked low by the reset, both Q7 and Q8 have just transitioned to low anyway.

The clock into U7 is capacitor coupled. Why? There is no DC reference for the input.

The output from the analog switch has a unknown value capacitor to GND. Why?

The clock into U7 (and hence the data rate into the D/A, does not change when the analog switch is switched. It is tied to the 15.5 kHz input at all times. This is the reason the circuit is not doing what you want. In 60 Hz mode you are terminating the data cycle half way through the full pattern. To have the D/A make the full pattern in half the time, the data needs to arrive twice as fast. This means doubling the clock freq into U7, not simply resetting it sooner.

ak
 
U4 - the connection between Q9 and the reset input does not do anything. When Q9 goes high, forces a reset, and then is yanked low by the reset, both Q7 and Q8 have just transitioned to low anyway.

The clock into U7 is capacitor coupled. Why? There is no DC reference for the input.

The output from the analog switch has a unknown value capacitor to GND. Why?

The clock into U7 (and hence the data rate into the D/A, does not change when the analog switch is switched. It is tied to the 15.5 kHz input at all times. This is the reason the circuit is not doing what you want. In 60 Hz mode you are terminating the data cycle half way through the full pattern. To have the D/A make the full pattern in half the time, the data needs to arrive twice as fast. This means doubling the clock freq into U7, not simply resetting it sooner.

ak
Thanks for your reply ak, those capacitors are not in use and nothing is installed in those locations. Will see if I can try to double my frequency.
 
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