except that I didn't implement the NAND gate buffer. Instead I'm trying to use just a 2n7000 N-FET (common source configuration with a 10K drain pull-up). The problem is that I'm seeing substantial glitches (~ .5 V) on the up transitions and the rise time is now very noticable. The high-to-low transitions are fine.
I'd like to square up the output signal as much as possible without using another CMOS IC. Any suggestions? Should I use a different transistor? smaller pull-up? add a cap somewhere?
For reference, here's the associated article for the schematic:
Thanks for the pointers, but I'm not using the 4011. I've replaced it with a 2n7000, and I'm getting about .5 V overshoot on the up-transitions (but no ringing). Also, FWIW, I'm using a 5V supply. I'd like not to resort to a 14-pin IC, although any CMOS Schmitt trigger gate would work very well.
I've change it to a source follower, and I'm getting a much cleaner signal, although it's only 2.5V signal instead of a 4.5V signal. Still, I'd like to understand the issues around the original circuit. I'm pretty sure the overshoot is causing extra counts to be registered by my frequency counter.
On the input side I'm connecting it to various LC tanks I'm toying with, the present one being an antenna for lightning detection and direction determination. On the output side I'm just connecting it to a frequency counter.
On the input side I'm connecting it to various LC tanks I'm toying with, the present one being an antenna for lightning detection and direction determination. On the output side I'm just connecting it to a frequency counter.