About make an audio power amplifier.

[spec]

What about (10k/2) + 10k =15k???

Very good.

I thought that it was important to make R16 as low as possible in the interests of good frequency response and low noise, but on reflection I realise the this is only a low frequency path so your resistor values will be fine.

Preamp schematic updated

spec

 

[Tony Stewart]

I already have 10000uF old Epcos cap (extract from old amplifier).

OK.. Then with 0.1F and 2 Ohm coil resistance, T=0.2sec response or 1 second charge time to 90% and ripple V will be very low. but crest factor on peak current very high. Measure ESR on Cap. otherwise thermal failure. unless limited by extra RLC filter.

 

[Tony Stewart]

Cooler speed controller using NTC-MF52AT 10K:
View attachment 99222

As @AGuru said your NTC control is wrong direction. Also Resistor values are too high to guarantee tight regulation, and saturation of output stage.
I changed all values for many reasons,. The cap also serves to pulse the fan on power up.
It works for NTC from 7K to 5KΩ which keeps it cooler with tighter regulation. YOu can make small adjustments to Re for start temp but 1K is too large when PNP saturates hFE approaches 10 and cannot drive full speed.

my Interactive java simulation here

 

[Nikolai Petrenko]

Preamp schematic updated

OK, I see. Fortunately, I haven't bought resistors yet.

 

[Tony Stewart]

Update:

Unfortunately , this simple design has no DC offset control or AC crossover temperature compensation. So good luck. Naturally DC offset will occur due to mismatched base impedance in the differential front end.

As I indicated before, unless you have loose tolerances to distortion, you may want to actually Define your specs up front as every good designer learns. Then when you test you can verify if your design meets the spec and learn to communicate your requirements accurately instead of taking hundreds of blog entries to get around to what you need to know. You learn how to write specs by reading them and use same format and then choosing what is important being specific with your goals and budget. Then we can "cut to the chase" as they say. the biggest question in our minds is how much do you know and are you willing to "make or buy" ( used) or just make your mistakes and learn the hard way. Often time and money is wasted by not being clear in your requirements with a design spec.

a better way. for DC offset and crossover bias optimization. Optimal is a tradeoff between excess heat or low efficiency ( class A) and large crossover distortion at changing output levels due to thermal drift in Vbe.

 

[Tony Stewart]

https://www.electro-tech-online.com/attachments/100w-png.99145/ [/QUOTE]

Unfortunately , this simple 60W PA design has no DC offset control or AC crossover temperature compensation. So good luck. Naturally DC offset will occur due to mismatched base impedance in the differential front end.

As I indicated before, unless you have loose tolerances to distortion, you may want to actually Define your specs up front as every good designer learns. Then when you test you can verify if your design meets the spec and learn to communicate your requirements accurately instead of taking hundreds of blog entries to get around to what you need to know. You learn how to write specs by reading them and use same format and then choosing what is important being specific with your goals and budget. Then we can "cut to the chase" as they say. the biggest question in our minds is how much do you know and are you willing to "make or buy" ( used) or just make your mistakes and learn the hard way. Often time and money is wasted by not being clear in your requirements with a design spec.

a better way. for DC offset and crossover bias optimization. Optimal is a tradeoff between excess heat or low efficiency ( class A) and large crossover distortion at changing output levels due to thermal drift in Vbe and 4:1 variations in hFE.

 

[Nikolai Petrenko]

As I indicated before, unless you have loose tolerances to distortion, you may want to actually Define your specs up front as every good designer learns. Then when you test you can verify if your design meets the spec and learn to communicate your requirements accurately instead of taking hundreds of blog entries to get around to what you need to know. You learn how to write specs by reading them and use same format and then choosing what is important being specific with your goals and budget. Then we can "cut to the chase" as they say. the biggest question in our minds is how much do you know and are you willing to "make or buy" ( used) or just make your mistakes and learn the hard way. Often time and money is wasted by not being clear in your requirements with a design spec.

Thank, you have taught me a lot just after a short time.

 

[Nikolai Petrenko]

a better way. for DC offset and crossover bias optimization. Optimal is a tradeoff between excess heat or low efficiency ( class A) and large crossover distortion at changing output levels due to thermal drift in Vbe.

Heat will not be a big problem.

 

[Tony Stewart]

No but drifting crossover distortion may be when cool, then thermal runaway risk exists if biased too much. Thermal runaway is mitigated by the 0.33 Ohm emitter resistors, so if the voltage drop in Vbe becomes less than the voltage rise due to current across the Re, you get more DC bias which leads to more Vbe drop and more Ic leading to thermal runaway and self destruction.

The risk is low due to a healthy large Re, but still exists at worst case output power loading. This emitter Re also compromises your dampening factor or inverse of load regulation as the bass reflex pushes current in the opposite direction when a change in voltage occurs at series resonance. Thus your dampening factor depends on negative feedback gain, and output impedance with minimum at 4 ohms ( about twice DCR of coils) Zsp*Av/(Re+Rbe)= 4*23/(0.33+?)< 273 which in between minimum and great (100-1000).

I have found the optimal DF, thermal runaway point uses temp compensated bias like Nakamichi with the minimum Re just slightly higher than the Rbe bulk resistance which one can compute from datasheets above saturation. The same is true for wiring Power LEDS in parallel, by adding an equalization R, often just long wire resistance to compensate for variations in ESR of the power diode, which is approximately ESR<=1/W power rating of the diode junction ( true for any type of diode from 75 mW to 750W or whatever... they dont teach you this in school or industry) This assumes adequately low Rja thermal resistance which affects the safety margin. I choose 10 % variation of Rbe which depends on quality of parts and heatsink Rja.

When current sharing any parallel devices, the product of Rja and Vpn for the diode based on -mV/'C and power capacity of Vbe or Vpn for power LEDs will determine value of series R, such 0.1Ω for 1W LEDs or 0.33Ω for Rbe for your PA based on power rating of Vbe junction. However I choose LEDs with tight tolerances on Vf, so wire resistance is often sufficient.

This means if you had temp and offset compensation, you could reduce losses and increase DF.


FYI only on your next bigger and better design,!

edit...
What this also means is your power supply must be lower ESR than your PA output impedance otherwise distortion and DF are degraded.

Since Zo = (Re (+Rbe))/ Av = 0.33/23 =23 mΩ. , which includes ESR of your big cap and wire R and inductive reactance.

Since Rbe rises rapidly with temp, its value with AC+DC current approaching your Re fix value, then add your ESR of V+- , from Cap aging and layout, your DF will be much lower than theoretical max of 273 and in fact may drop below 100 unless your verify ESR of the nice big cap.

edit.. new epcos 100k uF 50V caps are rated at 6.8mΩ when new. This means your bridge diode peak current or Pd may be exceeded if not designed for power-on surge time. I would verify ESR, bridge ESR, compute RC energy during power on and consider surge limiter. Some use relay bypass over fixed R, others use inexpensive NTC ICL's for desired current limits. Without this design improvement, stress factors on Cap, bridge reliability reduce MTBF rapidly. Consider 30Vp turn on into xx mΩ total ESR will saturate transformer secondary thus putting heat stress on turnon to part with highest ESR. When secondary saturates, Lm drops dramatically and causes Transformer wires to buzz on startup adding more vibration and heat stress to wire insulation. so consider ESR in everything on overall design and consider Short limiter and or short Circuit protection in your design. Some use fan cooled polyfuse to detect fan failure, others tach voltage or proper convection design.

 

[Tony Stewart]

much more design details need to be checked to ensure robust overall design verification.

 

[Tony Stewart]

Ideally Q5 is thermally mounted with Q6,7 for compensation, or thermistor can be used.
The Vbe which affects output bias is from drivers Q6,Q7.

For reference there are graphs on Q8,9 which you can compute ESR at worst case hot currents from incremental slope of delta V/ delta I. At Ic:Ib=10:1 and Ic=3A, at Tj=150'C, PNP Rbe~0.1Ω which means DF is now 23*4Ω/0.43= 213 ok but excluding ESR of Vcc and speaker wires. ...which is why beefy litz wire is best for speakers for bass response.

 

[Nikolai Petrenko]

No but drifting crossover distortion may be when cool, then thermal runaway risk exists if biased too much. Thermal runaway is mitigated by the 0.33 Ohm emitter resistors, so if the voltage drop in Vbe becomes less than the voltage rise due to current across the Re, you get more DC bias which leads to more Vbe drop and more Ic leading to thermal runaway and self destruction.

The risk is low due to a healthy large Re, but still exists at worst case output power loading. This emitter Re also compromises your dampening factor or inverse of load regulation as the bass reflex pushes current in the opposite direction when a change in voltage occurs at series resonance. Thus your dampening factor depends on negative feedback gain, and output impedance with minimum at 4 ohms ( about twice DCR of coils) Zsp*Av/(Re+Rbe)= 4*23/(0.33+?)< 273 which in between minimum and great (100-1000).

I have found the optimal DF, thermal runaway point uses temp compensated bias like Nakamichi with the minimum Re just slightly higher than the Rbe bulk resistance which one can compute from datasheets above saturation. The same is true for wiring Power LEDS in parallel, by adding an equalization R, often just long wire resistance to compensate for variations in ESR of the power diode, which is approximately ESR<=1/W power rating of the diode junction ( true for any type of diode from 75 mW to 750W or whatever... they dont teach you this in school or industry) This assumes adequately low Rja thermal resistance which affects the safety margin. I choose 10 % variation of Rbe which depends on quality of parts and heatsink Rja.

When current sharing any parallel devices, the product of Rja and Vpn for the diode based on -mV/'C and power capacity of Vbe or Vpn for power LEDs will determine value of series R, such 0.1Ω for 1W LEDs or 0.33Ω for Rbe for your PA based on power rating of Vbe junction. However I choose LEDs with tight tolerances on Vf, so wire resistance is often sufficient.

This means if you had temp and offset compensation, you could reduce losses and increase DF.


FYI only on your next bigger and better design,!

edit...
What this also means is your power supply must be lower ESR than your PA output impedance otherwise distortion and DF are degraded.

Since Zo = (Re (+Rbe))/ Av = 0.33/23 =23 mΩ. , which includes ESR of your big cap and wire R and inductive reactance.

Since Rbe rises rapidly with temp, its value with AC+DC current approaching your Re fix value, then add your ESR of V+- , from Cap aging and layout, your DF will be much lower than theoretical max of 273 and in fact may drop below 100 unless your verify ESR of the nice big cap.

edit.. new epcos 100k uF 50V caps are rated at 6.8mΩ when new. This means your bridge diode peak current or Pd may be exceeded if not designed for power-on surge time. I would verify ESR, bridge ESR, compute RC energy during power on and consider surge limiter. Some use relay bypass over fixed R, others use inexpensive NTC ICL's for desired current limits. Without this design improvement, stress factors on Cap, bridge reliability reduce MTBF rapidly. Consider 30Vp turn on into xx mΩ total ESR will saturate transformer secondary thus putting heat stress on turnon to part with highest ESR. When secondary saturates, Lm drops dramatically and causes Transformer wires to buzz on startup adding more vibration and heat stress to wire insulation. so consider ESR in everything on overall design and consider Short limiter and or short Circuit protection in your design. Some use fan cooled polyfuse to detect fan failure, others tach voltage or proper convection design.

Oh I see.

 

[Nikolai Petrenko]

View attachment 100101 View attachment 100102 Ideally Q5 is thermally mounted with Q6,7 for compensation, or thermistor can be used.
The Vbe which affects output bias is from drivers Q6,Q7.

For reference there are graphs on Q8,9 which you can compute ESR at worst case hot currents from incremental slope of delta V/ delta I. At Ic:Ib=10:1 and Ic=3A, at Tj=150'C, PNP Rbe~0.1Ω which means DF is now 23*4Ω/0.43= 213 ok but excluding ESR of Vcc and speaker wires. ...which is why beefy litz wire is best for speakers for bass response.

Sorry but TIP41C/TIP42C aren't my choice.

 

[Nikolai Petrenko]

Halo everyone,
I need a check about my final PCB layout to ensure that I can ironing it soon:

 

[Nikolai Petrenko]

The toroid transformer here:
**broken link removed**
**broken link removed**

 

[spec]

Nice

 

[Tony Stewart]

Sorry but TIP41C/TIP42C aren't my choice.

Regardless of Transistor , you ignored the other characteristics, unless you take care with ESR on each part, your DF will cumulatively degrade from theoretical max defined.

What is the ESR (effectively ) of torroid?

DCR<50 milliOhms is what is desired for good DF to prevent bass distortion for this power level. i.e. with 24 Vp and speaker Zmin of 4 Ohms below 50 Hz bass at 6Ap results in 0.05x6=0.3Vp of distortion.

 

[Nikolai Petrenko]

What is the ESR (effectively ) of torroid?

I don't know, my multimeter dead recently.

 

[Nikolai Petrenko]

Nice

But I need to rewinding the secondary coil, because origin is dual 42VAC, while my requirement is dual 25-26VAC.

 

[spec]

But I need to rewinding the secondary coil, because origin is dual 42VAC, while my requirement is dual 25-26VAC.

That is a nuisance, but no big deal providing the secondary is wound over the primary.

spec

corrected