40106 Schmitt trigger

[Jules]

Hi there, Interesting site. I want to us a hex NAND gate Schmitt to get a monostable pulse, a delay, and then two astable pulses from the same chip. Is this possible? Also, can I gate the two circuits so that the astable is switched by the monostable? I know the 555 is often used in this way, but the CMOS quiescent current is what I need for long-term battery use. Even the 7555 has a higher supply!
I need the monostable to be on for about one second, allowing just two pulses from the astable in this time.
The complete pulse chain I need is -
1) monostable on for one second
2) delay of about 1/2 second, no pulses (from a second monostable?)
3) astable giving two pulses of about 1/2 second each, separated by 1/2 second.
4) return to step 1 to await next trigger

I also have a question about NAND gate function. Why are TWO gates needed to make an astable on a standard NAND chip like the 4011, but only ONE gate on the 4093 and 40106 Schmitt NAND gates?

Thanks for your help,
Julian Silverton

 

[Russlk]

The attached circuit should generate the pulse train you want, but you have to work out the R-C values. Use low leakage caps, not electrolytic type.

The schmitt trigger by definition has two stable states, so it can oscillate between those states with one unit. The attached circuit does not use a schmitt.

 

[Roff]

I'm posting this simplified circuit in response to a PM from Jules. I haven't tested it. Jules, you'll have to calculate time constants from the datasheet and connect pins I haven't shown. The input pin that is grounded is A1 (positive edge trigger). Pick your own NAND gate. Tie inputs of unused gates to one of the supply rails. If you have problems, post your question here. Be careful about supply voltage if mixing logic families.

This could be done with a clock, a counter, and some logic, but this seems simpler and more flexible for what I think you want.

Good luck!

NOTE: This circuit does not do what Jules requested above. It does what he requested in his PM. Jules, it would help if you could repeat that here.

 

[laroche73]

cascaded delays

I'm also posting a simplified circuit in response to a PM from Jules. This topic has come up before, in the hay baler thread for example. I also suggested chained monostables to generate the delays (using the quad 558 timer, for ex.), but thought a sequence generator based on a CD4017 (or 4022) might be simpler :wink:. Maybe not.

In the circuit shown below, the 4017 sequences through the delays. The cap stays the same for all timing periods, but a different timing resistor is switched in each time the 4017 increments. This approach works best when the delays have the same order of magnitude. The diodes keep the outputs from interferring with one another. Diode Dx provides a quick discharge path when the schmitt trigger output is low, much like the discharge transistor in a 555 monostable does. The second NAND gate is used as a negative-logic OR, and provides rising edge clocks for the 4017. The external trigger input should pulse low briefly, as in triggering a 555 monostable. For a high-going logic trigger, use the remaining section of the NAND package to invert the signal. The 4017's "0" output keeps any leakage current from Dx from charging up the cap during the idle state. The cap charges from ~ GND when output "1" is active, and from the schmitt triggers' lower trip point for outputs "2" and above. Note that the short discharge cycle adds to the delay of each stage except output "1", and should be accounted for. It's not shown on the schematic, but output "6" (pin 5) should be tied back to the 4017's Reset pin (pin 15).

The outputs should sequence as follows:

0) idle state
1) initial pulse (pulse length wasn't specified)
2) 5 sec delay
3) 1/2 sec pulse
4) 1 sec delay
5) 1/2 sec pulse
6) reset, back to idle state

The necessary 4017 outputs would need to be OR'd together for a single output line.

This circuit hasn't been tested, it's a back of the envelope design and may have problems I haven't considered. To improve it, I'd probably put an edge-detector (XOR) between the schmitt trigger and the 4017s clock. Then, successive 4017 outputs could control both the schmitt triggers' charge and discharge cycles (alternating diode polarities where needed).

A small micro is another good alternative, if you're willing to invest some time in the learning curve. Many of the 8-pin micros have internal oscillators, and can generate any arbitrary sequence of time delays.

 

[Roff]

Claude, that's a really slick idea! You're not as dumb as I look. :lol:

 

[nettron1000]

This topic has come up before, in the hay baler thread for example. I also suggested chained monostables to generate the delays (using the quad 558 timer, for ex.), but thought a sequence generator based on a CD4017 (or 4022) might be simpler . Maybe not.

Ingenious circuit idea Laroche, wish you had posted it in the haybaler thread. Now i feel like a fool. . I got sidetracked by other things and never did get back to it.

 

[laroche73]

cascaded delays

Thanks for the good feedback, guys . After re-visiting the hay baler thread, I have to say the idea is similar to the one Mechie proposed. - Claude

 

[Jules]

Thanks for feedback on monostable delay circuit

Thanks for all the ideas. I'm working through them