verilog, verilogger, file with 'v' extension

[PG1995]

Hi

Yesterday, I borrowed a book from someone and the book had a companion CD. Out of curiosity, I checked out the CD's contents and also read the introduction pages of the book. The book said the CD contained Verilog HDL files for some of the examples in the book with the software Verilogger Pro, Waveform Viewer, etc.

The files had 'v' extension which I wasn't able to open even after installing the Verilogger Pro. But I was successful in opening the file with the Notepad. The code below had the contents of one of the files.

After little searching on the net I came to know that Verilog is hardware description language (HDL) and Verilogger Pro is a simulator. Does it mean that if a write a certain code then the simulator can tell me how that code will be implemented like which component you will need etc.? Is HDL primarily used for digital logic?

How do I open that 'v' extension file?

Please help me with the queries above. Thank you very much.

Regards
PG

 

[BrownOut]

Does it mean that if a write a certain code then the simulator can tell me how that code will be implemented like which component you will need etc.?

No. The simulator simulates your code. You need to know what function your code implements, and you have to create a "testbench" which provides the necessary stimulus and records results.

Is HDL primarily used for digital logic?

Yes.

How do I open that 'v' extension file?

It's a simple text file. Any text editor should open it.

 

[PG1995]

Thank you, BrownOut, for the reply.

I have MultiSim and Circuit Wizard programs. They both let you use gates in electric circuits. But I don't think they do what I describe below. Do they?

I want a program in which I can drag-and-drop the gates etc. and then simply describe the inputs to see what the output should be.

For example, suppose I have created the following circuit after dragging-and-dropping the NAND gates, then I state what the inputs would be to A, B, and C, and then the program tells me the output at Q.

**broken link removed**

 

[BrownOut]

I don't use Multisim or Circuit Wizard. In the past, most digital circuit simulators had a way to enter symbols for conversion to VHDL or verilog for simulation. I've never used those features though.

 

[PG1995]

Hi

Is it possible to assign value to a variable using keyboard in Verilog? Like in C++, "cout" and "cin" can be used for this purpose. Thank you

 

[kubeek]

No, reading "live" input from console is not supported. However you can read input from a file.
Some simulators let you click in the input waveform, some require you to write a file that generates the stimulus for the circuit.

 

[PG1995]

Thanks, kubeek.

No, reading "live" input from console is not supported.

Please don't my asking this again but are you really sure about this? Thank you.

Regards
PG

 

[kubeek]

Yes I am pretty sure. Verilog is geared towards running a simulation that is already prepared, along with all the checks and asserts so that you only run it and wait for the final result. Then if you are trying to track a bug you can look at the waveforms, but all that is done with already made inputs.

 

[PG1995]

Hi

Could you please help me with the code below? It's totally messed up. It does compile but logically it's all wrong. Where am I going wrong? Thanks.

//4-bit 2x1 Mux

module two_to_1_mux(Y,A,B,Sel,En);

input [3:0]A;   
input [3:0]B;
input Sel,En;
output [3:0]Y;
reg [3:0]Y;   

always @(En)   
 
  if (Sel==0)
   
  assign Y = A;

  else
   
  assign Y = B;
endmodule

//stimulus

module testbench;

  reg [3:0]A;
  reg [3:0]B;
  reg Sel, En;
  wire [3:0]Y;

  two_to_1_mux mux(Y,A,B,Sel,En);

  initial
  begin
  A<=4'b1111;
  B<=4'b0000;
  En<=1;
  Sel<=0;
  #20
  Sel<=1;
  #20 $finish;
  end

endmodule

 

[kubeek]

I think you are missing A and B in your sensitivity list, this way Y is updated only when En changes.

 

[PG1995]

Thank you, kubeek.

Unfortunately, it's still not working. I have attached the screenshot of output. Could you please give the code a proper look?

Thanks.

 

[kubeek]

I guess what you want is

//4-bit 2x1 Mux

module two_to_1_mux(Y,A,B,Sel,En);

input [3:0]A; 
input [3:0]B;
input Sel,En;
output [3:0]Y;
reg [3:0]Y; 

always @(En, Sel, A, B) 
  if(En==1)begin
  if (Sel==0)
  assign Y = A;
  else
  assign Y = B;
  end
endmodule

//stimulus

module testbench;

  reg [3:0]A;
  reg [3:0]B;
  reg Sel, En;
  wire [3:0]Y;

  two_to_1_mux mux(Y,A,B,Sel,En);

  initial
  begin
  A<=4'b1111;
  B<=4'b0000;
  En<=1;
  Sel<=0;
  #20
  Sel<=1;
  #20 $finish;
  end
endmodule

but I would rather write it as follows, i am not sure if assign statement inside always block is synthesisable, this way it definitely will work:

always @(En, Sel, A, B) 
  if(En==1)begin
  if (Sel==0)
  Y <= A;
  else
  Y <= B;
  end
endmodule

 

[PG1995]

Thank you, kubeek.

I hope the code is correct now. I'm using the code given below.

Could you please help me with these queries related to the output diagram for the code? I'm using Verilogger program. Thanks a lot.

//4-bit 2x1 Mux

module two_to_1_mux(Y,A,B,Sel,En);

input [3:0]A;
input [3:0]B;
input Sel,En;
output [3:0]Y;
reg [3:0]Y;

always @(En or Sel or A or B)
  if(En==1)begin
  if (Sel==0)
  Y <= A;
  else
  Y <= B;
  end
endmodule


//stimulus

module testbench;

  reg [3:0]A;
  reg [3:0]B;
  reg Sel, En;
  wire [3:0]Y;

  two_to_1_mux mux(Y,A,B,Sel,En);

  initial
  begin
  A<=4'b1111;
  B<=4'b1010;
  En<=1;
  Sel<=0;
  #20
  Sel<=1;
  #20 $finish;
  end
endmodule

 

[kubeek]

I nevere used verilogger, so i can't really help you with the second question. Try right clicking the signal if there are some options.
As for the first one, since A, B and Y are buses with many bits, the program is showing them with two lines - this signifies that they are buses and their value is written there. If a single bit signal changes, then you see an edge like with the Sel signal.
When a bus changes state you need to show it somehow, and you can't show a single edge since that would not be true, there could be an edge going up or down on any of the bits, so you show it like a data block with value F has changed into a block with value A, and that double crossing shows where all those edges would be.

 

[PG1995]

Thank you, kubeek.

I was able to make the output diagram more understandable by following your suggestion - i.e. right clicking the signals.

Thanks.

 

[PG1995]

Hi again,

Suppose now I want to make a 4x1 multiplexer using three 2x1 multiplexer. I have the code written for 2x1 multiplexer in a file. How can I instantiate 2x1 multiplexers in a new file without copying the original code of 2x1 previously written? Please help me with it. Thanks.

 

[kubeek]

Just like you instantiated the single mutliplexer in that testbench, but you need to use dunnowhatitscalled type of instantiation where you assign each wire of the mux to a specific wire in your upper module. like this:

mux1 mux(.Y(y1), .A(in1), .B(in2), .Sel(sela), .En(en));
mux2 mux(.Y(y2), .A(in3), .B(in4), .Sel(sela), .En(en));
mux3 mux(.Y(y3), .A(y1), .B(y2), .Sel(selb), .En(en));

 

[kubeek]

Also I guess you might want to go through this tutorial https://www.asic-world.com/verilog/veritut.html

 

[PG1995]

Thanks.

This is what I was trying to do. I created a new project file titled four_to_one_mux. I have added the code file containing the code for 2x1 multiplexer to this project. Then, I created a new code file in the project titled four_one, and in this file I need to instantiate three 2x1 multiplexers using my previously written code. Am I going a right thing so far?

Actually I had already written few lines before I saw post #17 above but those lines didn't compile.

//4 to 1 mux using 2 to 1 muxs

two_to_1_mux mux1(Y1,A,B,SEL0,En);

two_to_1_mux mux2(Y2,C,D,SEL0,En);

two_to_1_mux mux3(Y3,Y1,Y2,SEL1,En);

Yes, that tutorial website is really good. I have been using it for some time now. Thanks.

PS: I need to use "include" directive.

Useful links:
1: https://wiresharklabs.wordpress.com/2013/03/27/chapter-5-combinational-logic/

 

[kubeek]

I don't think you need to use include directive, you just need to have the other files within the same project.
Yes that should be right. It seems I messed up the order of the instantiation, the correct is the way you have it - the instantiated module goes first and then the name of this instance.
It is better to use the explicit connections like .Y(Y1) because late when you change something in your code and mess up the order it will keep working and not break up, just because the order of the parameters changed.
Post your code, along with the errors you get.